def main(): parser = argparse.ArgumentParser( description="LiteX SoC Simulation utility") sim_args(parser) args = parser.parse_args() soc_kwargs = soc_core_argdict(args) builder_kwargs = builder_argdict(args) sys_clk_freq = int(1e6) sim_config = SimConfig() sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq) # Configuration -------------------------------------------------------------------------------- cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv")) # UART. if soc_kwargs["uart_name"] == "serial": soc_kwargs["uart_name"] = "sim" sim_config.add_module("serial2console", "serial") # ROM. if args.rom_init: soc_kwargs["integrated_rom_init"] = get_mem_data( args.rom_init, cpu.endianness) # RAM / SDRAM. soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size if args.integrated_main_ram_size: if args.ram_init is not None: soc_kwargs["integrated_main_ram_init"] = get_mem_data( args.ram_init, cpu.endianness) elif args.with_sdram: assert args.ram_init is None soc_kwargs["sdram_module"] = args.sdram_module soc_kwargs["sdram_data_width"] = int(args.sdram_data_width) soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity) if args.sdram_from_spd_dump: soc_kwargs["sdram_spd_data"] = parse_spd_hexdump( args.sdram_from_spd_dump) # Ethernet. if args.with_ethernet or args.with_etherbone: if args.ethernet_phy_model == "sim": sim_config.add_module("ethernet", "eth", args={ "interface": "tap0", "ip": args.remote_ip }) elif args.ethernet_phy_model == "xgmii": sim_config.add_module("xgmii_ethernet", "xgmii_eth", args={ "interface": "tap0", "ip": args.remote_ip }) elif args.ethernet_phy_model == "gmii": sim_config.add_module("gmii_ethernet", "gmii_eth", args={ "interface": "tap0", "ip": args.remote_ip }) else: raise ValueError("Unknown Ethernet PHY model: " + args.ethernet_phy_model) # I2C. if args.with_i2c: sim_config.add_module("spdeeprom", "i2c") trace_start = int(float(args.trace_start)) trace_end = int(float(args.trace_end)) # SoC ------------------------------------------------------------------------------------------ soc = SimSoC(with_sdram=args.with_sdram, with_ethernet=args.with_ethernet, ethernet_phy_model=args.ethernet_phy_model, with_etherbone=args.with_etherbone, with_analyzer=args.with_analyzer, with_i2c=args.with_i2c, with_sdcard=args.with_sdcard, with_spi_flash=args.with_spi_flash, with_gpio=args.with_gpio, sim_debug=args.sim_debug, trace_reset_on=trace_start > 0 or trace_end > 0, sdram_init=[] if args.sdram_init is None else get_mem_data( args.sdram_init, cpu.endianness), spi_flash_init=None if args.spi_flash_init is None else get_mem_data(args.spi_flash_init, "big"), **soc_kwargs) if args.ram_init is not None or args.sdram_init is not None: soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"]) if args.with_ethernet: for i in range(4): soc.add_constant("LOCALIP{}".format(i + 1), int(args.local_ip.split(".")[i])) for i in range(4): soc.add_constant("REMOTEIP{}".format(i + 1), int(args.remote_ip.split(".")[i])) # Build/Run ------------------------------------------------------------------------------------ def pre_run_callback(vns): if args.trace: generate_gtkw_savefile(builder, vns, args.trace_fst) builder_kwargs["csr_csv"] = "csr.csv" builder = Builder(soc, **builder_kwargs) builder.build(threads=args.threads, sim_config=sim_config, opt_level=args.opt_level, trace=args.trace, trace_fst=args.trace_fst, trace_start=trace_start, trace_end=trace_end, interactive=not args.non_interactive, pre_run_callback=pre_run_callback)
def main(): parser = argparse.ArgumentParser( description="Generic LiteX SoC Simulation") sim_args(parser) args = parser.parse_args() soc_kwargs = soc_sdram_argdict(args) builder_kwargs = builder_argdict(args) sys_clk_freq = int(1e6) sim_config = SimConfig() sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq) # Configuration -------------------------------------------------------------------------------- cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")] if soc_kwargs["uart_name"] == "serial": soc_kwargs["uart_name"] = "sim" sim_config.add_module("serial2console", "serial") if args.rom_init: soc_kwargs["integrated_rom_init"] = get_mem_data( args.rom_init, cpu.endianness) if not args.with_sdram: soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB if args.ram_init is not None: soc_kwargs["integrated_main_ram_init"] = get_mem_data( args.ram_init, cpu.endianness) else: assert args.ram_init is None soc_kwargs["integrated_main_ram_size"] = 0x0 soc_kwargs["sdram_module"] = args.sdram_module soc_kwargs["sdram_data_width"] = int(args.sdram_data_width) soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity) if args.sdram_from_spd_dump: soc_kwargs["sdram_spd_data"] = parse_spd_hexdump( args.sdram_from_spd_dump) if args.with_ethernet or args.with_etherbone: sim_config.add_module("ethernet", "eth", args={ "interface": "tap0", "ip": args.remote_ip }) if args.with_i2c: sim_config.add_module("spdeeprom", "i2c") trace_start = int(float(args.trace_start)) trace_end = int(float(args.trace_end)) # SoC ------------------------------------------------------------------------------------------ soc = SimSoC(with_sdram=args.with_sdram, with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, with_analyzer=args.with_analyzer, with_i2c=args.with_i2c, with_sdcard=args.with_sdcard, sim_debug=args.sim_debug, trace_reset_on=trace_start > 0 or trace_end > 0, sdram_init=[] if args.sdram_init is None else get_mem_data( args.sdram_init, cpu.endianness), **soc_kwargs) if args.ram_init is not None or args.sdram_init is not None: soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) if args.with_ethernet: for i in range(4): soc.add_constant("LOCALIP{}".format(i + 1), int(args.local_ip.split(".")[i])) for i in range(4): soc.add_constant("REMOTEIP{}".format(i + 1), int(args.remote_ip.split(".")[i])) # Build/Run ------------------------------------------------------------------------------------ builder_kwargs["csr_csv"] = "csr.csv" builder = Builder(soc, **builder_kwargs) for i in range(2): build = (i == 0) run = (i == 1) vns = builder.build(build=build, run=run, threads=args.threads, sim_config=sim_config, opt_level=args.opt_level, trace=args.trace, trace_fst=args.trace_fst, trace_start=trace_start, trace_end=trace_end) if args.with_analyzer: soc.analyzer.export_csv(vns, "analyzer.csv") if args.gtkwave_savefile: generate_gtkw_savefile(builder, vns, args.trace_fst)
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, with_rts_reset=False, with_led_chaser=True, spd_dump=None, **kwargs): platform = berkeleylab_marble.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Berkeley-Lab Marble", **kwargs) # CRG, resettable over USB serial RTS signal ----------------------------------------------- resets = [] if with_rts_reset: ser_pads = platform.lookup_request('serial') resets.append(ser_pads.rts) self.submodules.crg = _CRG(platform, sys_clk_freq, resets) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) if spd_dump is not None: ram_spd = parse_spd_hexdump(spd_dump) ram_module = SDRAMModule.from_spd_data(ram_spd, sys_clk_freq) print('DDR3: loaded config from', spd_dump) else: ram_module = MT8JTF12864(sys_clk_freq, "1:4") # KC705 chip, 1 GB print( 'DDR3: No spd data specified, falling back to MT8JTF12864') self.add_sdram( "sdram", phy=self.ddrphy, module=ram_module, # size=0x40000000, # Limit its size to 1 GB l2_cache_size=kwargs.get("l2_size", 8192), with_bist=kwargs.get("with_bist", False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRGMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), tx_delay=0) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=True, software_debug=False) if with_etherbone: self.add_etherbone(phy=self.ethphy, buffer_depth=255) # System I2C (behing multiplexer) ---------------------------------------------------------- i2c_pads = platform.request('i2c_fpga') self.submodules.i2c = I2CMaster(i2c_pads) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def main(): parser = argparse.ArgumentParser( description="Generic LiteX SoC Simulation") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--threads", default=1, help="Set number of threads (default=1)") parser.add_argument("--rom-init", default=None, help="rom_init file") parser.add_argument("--ram-init", default=None, help="ram_init file") parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support") parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip") parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width") parser.add_argument("--sdram-init", default=None, help="SDRAM init file") parser.add_argument( "--sdram-from-spd-dump", default=None, help="Generate SDRAM module based on data from SPD EEPROM dump") parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address of SoC (default=192.168.1.50)") parser.add_argument( "--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server (default=192.168.1.100)") parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer support") parser.add_argument("--with-i2c", action="store_true", help="Enable I2C support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--trace", action="store_true", help="Enable Tracing") parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)") parser.add_argument("--trace-start", default=0, help="Cycle to start tracing") parser.add_argument("--trace-end", default=-1, help="Cycle to end tracing") parser.add_argument("--opt-level", default="O3", help="Compilation optimization level") args = parser.parse_args() soc_kwargs = soc_sdram_argdict(args) builder_kwargs = builder_argdict(args) sim_config = SimConfig(default_clk="sys_clk") # Configuration -------------------------------------------------------------------------------- cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")] if soc_kwargs["uart_name"] == "serial": soc_kwargs["uart_name"] = "sim" sim_config.add_module("serial2console", "serial") if args.rom_init: soc_kwargs["integrated_rom_init"] = get_mem_data( args.rom_init, cpu.endianness) if not args.with_sdram: soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB if args.ram_init is not None: soc_kwargs["integrated_main_ram_init"] = get_mem_data( args.ram_init, cpu.endianness) else: assert args.ram_init is None soc_kwargs["integrated_main_ram_size"] = 0x0 soc_kwargs["sdram_module"] = args.sdram_module soc_kwargs["sdram_data_width"] = int(args.sdram_data_width) soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity) if args.sdram_from_spd_dump: soc_kwargs["sdram_spd_data"] = parse_spd_hexdump( args.sdram_from_spd_dump) if args.with_ethernet or args.with_etherbone: sim_config.add_module("ethernet", "eth", args={ "interface": "tap0", "ip": args.remote_ip }) if args.with_i2c: sim_config.add_module("spdeeprom", "i2c") # SoC ------------------------------------------------------------------------------------------ soc = SimSoC(with_sdram=args.with_sdram, with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, with_analyzer=args.with_analyzer, with_i2c=args.with_i2c, with_sdcard=args.with_sdcard, sdram_init=[] if args.sdram_init is None else get_mem_data( args.sdram_init, cpu.endianness), **soc_kwargs) if args.ram_init is not None: soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) if args.with_ethernet: for i in range(4): soc.add_constant("LOCALIP{}".format(i + 1), int(args.local_ip.split(".")[i])) for i in range(4): soc.add_constant("REMOTEIP{}".format(i + 1), int(args.remote_ip.split(".")[i])) # Build/Run ------------------------------------------------------------------------------------ builder_kwargs["csr_csv"] = "csr.csv" builder = Builder(soc, **builder_kwargs) vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, opt_level=args.opt_level, trace=args.trace, trace_fst=args.trace_fst, trace_start=int(args.trace_start), trace_end=int(args.trace_end)) if args.with_analyzer: soc.analyzer.export_csv(vns, "analyzer.csv") builder.build(build=False, threads=args.threads, sim_config=sim_config, opt_level=args.opt_level, trace=args.trace, trace_fst=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))