def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
platform = vc707.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on VC707",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, toolchain="ise", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.timing_settings)
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = ac701.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = vc707.Platform()
# SoCCore ------------------------------------------------------------------_---------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
with_bist=False,
with_analyzer=False):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
ident="LiteDRAM bench on KC705",
ident_version=True,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(pads=PHYPadsReducer(
platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
with_bist=with_bist)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=256,
clock_domain="sys",
csr_csv="analyzer.csv")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
uart="crossover",
sys_clk_freq=int(125e6),
with_bist=False):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x10000,
integrated_rom_mode="rw",
csr_data_width=32,
uart_name=uart)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
with_bist=with_bist,
)
# UARTBone ---------------------------------------------------------------------------------
if uart != "serial":
self.add_uartbone(name="serial",
clk_freq=100e6,
baudrate=115200,
cd="uart")
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, toolchain="ise", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kc705.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KC705",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
cmd_latency=1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kc705.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
self.add_csr("ddrphy")
self.add_constant("DDRPHY_CMD_DELAY", 13)
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = vc707.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on VC707",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.V7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
cmd_latency=1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_etherbone=False,
with_rts_reset=False,
with_led_chaser=True,
spd_dump=None,
**kwargs):
platform = berkeleylab_marble.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Berkeley-Lab Marble",
**kwargs)
# CRG, resettable over USB serial RTS signal -----------------------------------------------
resets = []
if with_rts_reset:
ser_pads = platform.lookup_request('serial')
resets.append(ser_pads.rts)
self.submodules.crg = _CRG(platform, sys_clk_freq, resets)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
if spd_dump is not None:
ram_spd = parse_spd_hexdump(spd_dump)
ram_module = SDRAMModule.from_spd_data(ram_spd, sys_clk_freq)
print('DDR3: loaded config from', spd_dump)
else:
ram_module = MT8JTF12864(sys_clk_freq,
"1:4") # KC705 chip, 1 GB
print(
'DDR3: No spd data specified, falling back to MT8JTF12864')
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=ram_module,
# size=0x40000000, # Limit its size to 1 GB
l2_cache_size=kwargs.get("l2_size", 8192),
with_bist=kwargs.get("with_bist", False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
tx_delay=0)
if with_ethernet:
self.add_ethernet(phy=self.ethphy,
dynamic_ip=True,
software_debug=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# System I2C (behing multiplexer) ----------------------------------------------------------
i2c_pads = platform.request('i2c_fpga')
self.submodules.i2c = I2CMaster(i2c_pads)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self,
platform,
connector="pcie",
linerate=2.5e9,
use_gtp=True):
assert connector in ["pcie"]
sys_clk_freq = int(50e6)
# *********************************************************
# * SoC SDRAM *
# *********************************************************
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x1000,
uart_name="serial",
l2_size=0,
csr_data_width=32,
)
# *********************************************************
# * CRG *
# *********************************************************
self.submodules.crg = _CRG(platform, sys_clk_freq)
platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / sys_clk_freq)
# *********************************************************
# * DDR3 *
# *********************************************************
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# *********************************************************
# * Ethernet PHY *
# *********************************************************
eth_phy = LiteEthPHYRGMII(clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
with_hw_init_reset=False,
tx_delay=0e-9,
rx_delay=0e-9)
self.submodules.eth_phy = ClockDomainsRenamer("eth_tx")(eth_phy)
self.add_csr("eth_phy")
# *********************************************************
# * Ethernet Core *
# *********************************************************
eth_core = LiteEthUDPIPCore(phy=self.eth_phy,
mac_address=0x10e2d5000000,
ip_address="192.168.1.201",
clk_freq=125000000)
self.submodules.eth_core = ClockDomainsRenamer("eth_tx")(eth_core)
# *********************************************************
# * Etherbone bridge *
# *********************************************************
etherbone_cd = ClockDomain(
"etherbone") # similar to sys but need for correct
self.clock_domains += etherbone_cd # clock domain renaming
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp,
1234,
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
# *********************************************************
# * Timing constraints for Ethernet *
# *********************************************************
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
# *********************************************************
# * GTP Refclk *
# *********************************************************
if use_gtp:
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
# *********************************************************
# * GTP PLL *
# *********************************************************
qpll = GTPQuadPLL(refclk, refclk_freq, linerate)
print(qpll)
self.submodules += qpll
# *********************************************************
# * GTPs *
# *********************************************************
for i in range(2):
tx_pads = platform.request(connector + "_tx", i)
rx_pads = platform.request(connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
gtp.tx_enable = 0
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.cd_tx.clk, gtp.cd_rx.clk)
else:
gtp0_rx_cd = ClockDomain("gtp0_rx")
self.clock_domains += gtp0_rx_cd
self.comb += [
gtp0_rx_cd.clk.eq(ClockSignal("clk125")),
gtp0_rx_cd.rst.eq(ResetSignal("clk125"))
]
gtp1_rx_cd = ClockDomain("gtp1_rx")
self.clock_domains += gtp1_rx_cd
self.comb += [
gtp1_rx_cd.clk.eq(ClockSignal("clk125")),
gtp1_rx_cd.rst.eq(ResetSignal("clk125"))
]
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp1_rx_cd.clk,
gtp0_rx_cd.clk)
# *********************************************************
# * Time base *
# *********************************************************
time = Signal(32)
time_rx = Signal(32)
time_tx = Signal(32)
self.sync.clk125 += time.eq(time + 1)
self.specials += MultiReg(time, time_rx, "gtp0_rx")
self.specials += MultiReg(time, time_tx, "gtp1_rx")
# *********************************************************
# * RX Capture Pipeline *
# *********************************************************
RX_RING_BUFFER_BASE_ADDRESS = 0
RX_RING_BUFFER_SIZE = 0x100000
# Elaborate gtp0_ready
gtp0_ready = Signal()
if use_gtp:
self.specials += MultiReg(qpll.lock & self.gtp0.rx_ready,
gtp0_ready, "gtp0_rx")
else:
gtp0_ready.eq(0)
# Request RX DDR3 port
rx_port = self.sdram.crossbar.get_port("write", 256)
self.submodules.rx_capture = CapturePipeline(
"gtp0_rx", rx_port, RX_RING_BUFFER_BASE_ADDRESS,
RX_RING_BUFFER_SIZE)
self.add_csr("rx_capture")
self.add_csr("rx_capture_exerciser_mem")
self.add_csr("rx_capture_trigger_mem")
if use_gtp:
self.comb += self.gtp0.source.connect(self.rx_capture.sink,
omit={"valid"})
self.comb += [
self.rx_capture.sink.valid.eq(gtp0_ready
| self.rx_capture.simmode),
self.rx_capture.time.eq(time_rx),
]
# *********************************************************
# * TX Capture Pipeline *
# *********************************************************
TX_RING_BUFFER_BASE_ADDRESS = 0x100000
TX_RING_BUFFER_SIZE = 0x100000
# Elaborate gtp1_ready
gtp1_ready = Signal()
if use_gtp:
self.specials += MultiReg(qpll.lock & self.gtp1.rx_ready,
gtp1_ready, "gtp1_rx")
else:
gtp1_ready.eq(0)
# Request TX DDR3 port
tx_port = self.sdram.crossbar.get_port("write", 256)
self.submodules.tx_capture = CapturePipeline(
"gtp1_rx", tx_port, TX_RING_BUFFER_BASE_ADDRESS,
TX_RING_BUFFER_SIZE)
self.add_csr("tx_capture")
self.add_csr("tx_capture_exerciser_mem")
self.add_csr("tx_capture_trigger_mem")
if use_gtp:
self.comb += self.gtp1.source.connect(self.tx_capture.sink,
omit={"valid"})
self.comb += [
self.tx_capture.sink.valid.eq(gtp1_ready
| self.tx_capture.simmode),
self.tx_capture.time.eq(time_tx),
]
# *********************************************************
# * Recorder RX/TX *
# *********************************************************
self.comb += [
self.tx_capture.forced.eq(self.rx_capture.record),
self.rx_capture.forced.eq(self.tx_capture.record),
self.tx_capture.trigExt.eq(self.rx_capture.trigOut),
self.rx_capture.trigExt.eq(self.tx_capture.trigOut),
]
# *********************************************************
# * LEDs *
# *********************************************************
led_counter = Signal(32)
self.sync.gtp0_rx += led_counter.eq(led_counter + 1)
self.comb += platform.request("user_led", 0).eq(led_counter[24])
self.comb += platform.request("user_led", 1).eq(0)
self.comb += platform.request("user_led", 2).eq(0)
self.comb += platform.request("user_led", 3).eq(0)
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
eth_phy="rgmii",
with_led_chaser=True,
with_pcie=False,
**kwargs):
platform = ac701.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on AC701",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
size=0x40000000,
l2_cache_size=kwargs.get("l2_size", 8192))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# RGMII Ethernet PHY -------------------------------------------------------------------
if eth_phy == "rgmii":
# phy
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
# 1000BaseX Ethernet PHY ---------------------------------------------------------------
if eth_phy == "1000basex":
# phy
self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
qpll_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
refclk125 = self.platform.request("gtp_refclk")
refclk125_se = Signal()
self.specials += \
Instance("IBUFDS_GTE2",
i_CEB = 0,
i_I = refclk125.p,
i_IB = refclk125.n,
o_O = refclk125_se)
qpll = QPLL(refclk125_se, qpll_settings)
self.submodules += qpll
self.submodules.ethphy = A7_1000BASEX(
qpll_channel=qpll.channels[0],
data_pads=self.platform.request("sfp", 0),
sys_clk_freq=self.clk_freq)
self.add_ethernet(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, platform, connector="pcie", linerate=2.5e9):
assert connector in ["pcie"]
sys_clk_freq = int(50e6)
# SoCSDRAM ----------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x1000,
uart_name="serial",
l2_size=0,
csr_data_width=32,
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
platform.add_period_constraint(self.crg.cd_sys.clk, 1e9 / 100e6)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
# Ethernet ---------------------------------------------------------------------------------
# phy
eth_phy = LiteEthPHYRGMII(clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
with_hw_init_reset=False,
tx_delay=0e-9,
rx_delay=0e-9)
self.submodules.eth_phy = ClockDomainsRenamer("eth_tx")(eth_phy)
self.add_csr("eth_phy")
# core
eth_core = LiteEthUDPIPCore(phy=self.eth_phy,
mac_address=0x10e2d5000000,
ip_address="172.30.28.201",
clk_freq=125000000)
self.submodules.eth_core = ClockDomainsRenamer("eth_tx")(eth_core)
# etherbone bridge
etherbone_cd = ClockDomain(
"etherbone") # similar to sys but need for correct
self.clock_domains += etherbone_cd # clock domain renaming
self.comb += [
etherbone_cd.clk.eq(ClockSignal("sys")),
etherbone_cd.rst.eq(ResetSignal("sys"))
]
self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp,
1234,
cd="etherbone")
self.add_wb_master(self.etherbone.wishbone.bus)
# timing constraints
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk,
1e9 / 125e6)
self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk,
1e9 / 125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk,
self.eth_phy.crg.cd_eth_tx.clk)
# GTP RefClk -------------------------------------------------------------------------------
refclk = Signal()
refclk_freq = 100e6
refclk_pads = platform.request("pcie_refclk")
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=refclk_pads.p,
i_IB=refclk_pads.n,
o_O=refclk)
# GTP PLL ----------------------------------------------------------------------------------
qpll = GTPQuadPLL(refclk, refclk_freq, linerate)
print(qpll)
self.submodules += qpll
# GTPs -------------------------------------------------------------------------------------
for i in range(2):
tx_pads = platform.request(connector + "_tx", i)
rx_pads = platform.request(connector + "_rx", i)
gtp = GTP(qpll,
tx_pads,
rx_pads,
sys_clk_freq,
data_width=20,
clock_aligner=False,
tx_buffer_enable=True,
rx_buffer_enable=True)
gtp.add_stream_endpoints()
setattr(self.submodules, "gtp" + str(i), gtp)
platform.add_period_constraint(gtp.cd_tx.clk,
1e9 / gtp.tx_clk_freq)
platform.add_period_constraint(gtp.cd_rx.clk,
1e9 / gtp.rx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.cd_tx.clk,
gtp.cd_rx.clk)
# Record -------------------------------------------------------------------------------------
self.submodules.rx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 32, clock_domain="gtp0_rx"))
self.rx_dma_recorder.add_csr()
self.add_csr("rx_dma_recorder")
self.submodules.tx_dma_recorder = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port("write", 32, clock_domain="gtp1_rx"))
self.tx_dma_recorder.add_csr()
self.add_csr("tx_dma_recorder")
self.comb += [
self.rx_dma_recorder.sink.valid.eq(self.gtp0.source.valid),
self.rx_dma_recorder.sink.data.eq(
self.gtp0.source.payload.raw_bits()),
self.tx_dma_recorder.sink.valid.eq(self.gtp1.source.valid),
self.tx_dma_recorder.sink.data.eq(
self.gtp1.source.payload.raw_bits()),
]
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
with_pcie=False,
with_sata=False,
**kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KC705",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
(
"sfp2sata",
0,
Subsignal("tx_p", Pins("H2")),
Subsignal("tx_n", Pins("H1")),
Subsignal("rx_p", Pins("G4")),
Subsignal("rx_n", Pins("G3")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("sfp2sata"),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(150e6),
with_ethernet=False,
with_sata=False,
**kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on KC705",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# SATA (Experimental) ----------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litex.soc.interconnect import wishbone
from litesata.phy import LiteSATAPHY
from litesata.core import LiteSATACore
from litesata.frontend.arbitration import LiteSATACrossbar
from litesata.frontend.dma import LiteSATABlock2MemDMA
# IOs
_sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
(
"sfp",
0,
Subsignal("txp", Pins("H2")),
Subsignal("txn", Pins("H1")),
Subsignal("rxp", Pins("G4")),
Subsignal("rxn", Pins("G3")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("sfp"),
gen="gen1",
clk_freq=sys_clk_freq,
data_width=16)
# Core
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# Block2Mem DMA
bus = wishbone.Interface(data_width=32, adr_width=32)
self.submodules.sata_block2mem = LiteSATABlock2MemDMA(
user_port=self.sata_crossbar.get_port(),
bus=bus,
endianness=self.cpu.endianness)
self.bus.add_master("sata_block2mem", master=bus)
self.add_csr("sata_block2mem")
# Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk,
1e9 / 75e6)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk,
1e9 / 75e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_tx.clk)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(125e6),
with_ethernet=False,
cpu_variant="1c",
**kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_size"] = 0x10000
SoCCore.__init__(self,
platform,
clk_freq=sys_clk_freq,
cpu_cls=VexRiscvSMP,
cpu_variant=cpu_variant,
**kwargs)
# PLIC ------------------------------------------------------------------------------------
self.bus.add_slave("plic",
self.cpu.plicbus,
region=SoCRegion(origin=0xf0C00000,
size=0x400000,
cached=False))
# CLINT ------------------------------------------------------------------------------------
self.bus.add_slave("clint",
self.cpu.cbus,
region=SoCRegion(origin=0xf0010000,
size=0x10000,
cached=False))
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
pads=PHYPadsReducer(platform.request("ddram"), [1, 2]),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
cmd_latency=1)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True,
controller_settings=ControllerSettings(
cmd_buffer_buffered=False,
with_auto_precharge=False))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
clk_freq=self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# JTAG ---------------------------------------------------------------------------------
self.submodules.jtag = S7JTAG()
self.comb += self.cpu.jtag_clk.eq(self.jtag.tck)
self.comb += self.cpu.jtag_enable.eq(1)
self.comb += self.cpu.jtag_capture.eq(self.jtag.capture)
self.comb += self.cpu.jtag_shift.eq(self.jtag.shift)
self.comb += self.cpu.jtag_update.eq(self.jtag.update)
self.comb += self.cpu.jtag_reset.eq(self.jtag.reset)
self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi)
self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
ethernet_phy="rgmii",
**kwargs):
platform = ac701.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
# RGMII Ethernet PHY -------------------------------------------------------------------
if ethernet_phy == "rgmii":
# phy
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
# 1000BaseX Ethernet PHY ---------------------------------------------------------------
if ethernet_phy == "1000basex":
# phy
self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0)
self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0)
qpll_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
refclk125 = self.platform.request("gtp_refclk")
refclk125_se = Signal()
self.specials += \
Instance("IBUFDS_GTE2",
i_CEB = 0,
i_I = refclk125.p,
i_IB = refclk125.n,
o_O = refclk125_se)
qpll = QPLL(refclk125_se, qpll_settings)
self.submodules += qpll
self.submodules.ethphy = A7_1000BASEX(
qpll_channel=qpll.channels[0],
data_pads=self.platform.request("sfp", 0),
sys_clk_freq=self.clk_freq)
self.add_ethernet(phy=self.ethphy)
def __init__(self,
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
with_led_chaser=True,
with_pcie=False,
with_sata=False,
**kwargs):
platform = stlv7325.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on STLV7325",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
)
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT8JTF12864(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHY(
clock_pads=self.platform.request("eth_clocks", 0),
pads=self.platform.request("eth", 0),
clk_freq=self.clk_freq)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# TODO verify / test
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk=sata_refclk,
pads=platform.request(
"sata", 0),
gen="gen2",
clk_freq=sys_clk_freq,
data_width=16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led_n"),
sys_clk_freq=sys_clk_freq)
# I2C --------------------------------------------------------------------------------------
self.submodules.i2c = I2CMaster(platform.request("i2c"))
