def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') != 'lm32': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) # Ethernet --------------------------------------------------------------------------------- # Ethernet PHY self.submodules.ethphy = LiteEthPHY( platform.request("eth_clocks"), platform.request("eth")) self.add_csr("ethphy") # Ethernet MAC ethmac_win_size = 0x2000 self.submodules.ethmac = LiteEthMAC( phy = self.ethphy, dw = 32, interface = "wishbone", endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, ethmac_win_size) self.add_memory_region("ethmac", self.mem_map["ethmac"], ethmac_win_size, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if 'integrated_rom_size' not in kwargs and kwargs.get( 'cpu_type', 'lm32') != 'lm32': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) # Ethernet --------------------------------------------------------------------------------- # Ethernet Phy self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) self.add_csr("ethphy") # Ethernet Core etherbone_mac_address = 0x10e2d5000000 etherbone_ip_address = "192.168.100.50" self.submodules.ethcore = LiteEthUDPIPCore( phy=self.ethphy, mac_address=etherbone_mac_address, ip_address=etherbone_ip_address, clk_freq=self.clk_freq) # Etherbone Core self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 25e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 25e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, platform, *args, **kwargs): BaseSoC.__init__(self, platform, *args, **kwargs) self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), self.clk_freq) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") # FIXME: This is probably too tight? self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk) self.platform.add_platform_command( """ # FIXME: ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have # been found that are not placed at an optimal clock IOB / BUFGMUX site pair. # The clock IOB component <eth_clocks_rx> is placed at site <K15>. NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE; # The IOB component <eth_clocks_tx> is placed at site <K16>. NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE; """, eth_clocks_rx=platform.lookup_request("eth_clocks").rx, eth_clocks_tx=platform.lookup_request("eth_clocks").tx, )
def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if 'integrated_rom_size' not in kwargs and kwargs.get( 'cpu_type', 'lm32') == 'or1k': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") #self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 40.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 40.0) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs): BaseSoc.__init__(self, **kwargs) # ethernet PHY and UDP/IP stack mac_address = 0x10e2d5001000 ip_address = "192.168.1.50" self.submodules.ethphy = LiteEthPHY( self.platform.request("eth_clocks"), self.platform.request("eth"), self.clk_freq, # avoid huge reset delay in simulation with_hw_init_reset="synth" in argv) self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq) # MAC = wishbone slave = to let the CPU talk over ethernet # self.submodules.ethmac = LiteEthMAC( # phy=self.ethphy, dw=32, interface="wishbone", # endianness="little", with_preamble_crc=False # ) # self.add_wb_slave( # mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus # ) # self.add_memory_region( # "ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000 # ) # Etherbone = wishbone master = read and write registers remotely self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus)
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHY( self.platform.request("eth_clocks"), self.platform.request("eth"), clk_freq=self.clk_freq) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.crg.cd_sys.clk.attr.add("keep") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, ident="LiteDRAM bench on KC705", ident_version=True, integrated_rom_size=0x10000, integrated_rom_mode="rw", uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.K7DDRPHY(pads=PHYPadsReducer( platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], with_bist=with_bist) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), clk_freq=self.clk_freq) self.add_etherbone(phy=self.ethphy) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: from litescope import LiteScopeAnalyzer analyzer_signals = [self.ddrphy.dfi] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, depth=256, clock_domain="sys", csr_csv="analyzer.csv") # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, **kwargs): BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) self.submodules.ethphy = LiteEthPHY( self.platform.request("eth_clocks"), self.platform.request("eth"), clk_freq=self.clk_freq) self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) # Ethernet --------------------------------------------------------------------------------- # phy self.submodules.ethphy = LiteEthPHY( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), clk_freq = self.clk_freq) self.add_csr("ethphy") # mac self.submodules.ethmac = LiteEthMAC( phy = self.ethphy, dw = 32, interface = "wishbone", endianness = self.cpu.endianness) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk)
def __init__(self, revision, sys_clk_freq=int(50e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = pano_logic_g2.Platform(revision=revision) if with_etherbone: sys_clk_freq = int(125e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Pano Logic G2", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_ethernet or with_etherbone) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHY( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), clk_freq = sys_clk_freq, with_hw_init_reset = False) self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') != 'lm32': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) # Ethernet PHY self.submodules.ethphy = LiteEthPHY( platform.request("eth_clocks"), platform.request("eth")) self.clk_freq)
def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth")) self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac")
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x10000, integrated_rom_mode="rw", csr_data_width=32, uart_name=uart) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) self.add_csr("crg") # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram( "sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], with_bist=with_bist, ) # UARTBone --------------------------------------------------------------------------------- if uart != "serial": self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart") # Etherbone -------------------------------------------------------------------------------- self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), clk_freq=self.clk_freq) self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- from litex.soc.cores.led import LedChaser self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, *args, **kwargs): # Need a larger integrated ROM on or1k to fit the BIOS with TFTP support. if kwargs.get('cpu_type', 'lm32') != 'lm32': kwargs['integrated_rom_size'] = 0x10000 BaseSoC.__init__(self, platform, *args, **kwargs) # Ethernet --------------------------------------------------------------------------------- # Ethernet PHY self.submodules.ethphy = LiteEthPHY( clock_pads=platform.request("eth_clocks"), pads=platform.request("eth"), clk_freq=self.clk_freq) self.add_csr("ethphy") # Ethernet MAC ethmac_win_size = 0x2000 self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, ethmac_win_size) self.add_memory_region("ethmac", self.mem_map["ethmac"], ethmac_win_size, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") # timing constraints self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") # FIXME: This is probably too tight? self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) self.platform.add_platform_command( """ # FIXME: ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have # been found that are not placed at an optimal clock IOB / BUFGMUX site pair. # The clock IOB component <eth_clocks_rx> is placed at site <K15>. NET "{eth_clocks_rx}" CLOCK_DEDICATED_ROUTE = FALSE; # The IOB component <eth_clocks_tx> is placed at site <K16>. NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE; """, eth_clocks_rx=platform.lookup_request("eth_clocks").rx, eth_clocks_tx=platform.lookup_request("eth_clocks").tx, )
def __init__(self, platform, clk_freq=int(166e6), mac_address=0x10e2d5000000, ip_address="192.168.1.50"): sys_clk_freq = int((1 / (platform.default_clk_period)) * 1e9) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="LiteEth Base Design", with_timer=False) # Serial Wishbone Bridge serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200) self.submodules += serial_bridge self.add_wb_master(serial_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # Wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus) # Ethernet PHY and UDP/IP stack self.submodules.ethphy = ethphy = LiteEthPHY( clock_pads=platform.request("eth_clocks"), pads=platform.request("eth"), clk_freq=clk_freq) self.add_csr("ethphy") self.submodules.ethcore = ethcore = LiteEthUDPIPCore( phy=ethphy, mac_address=mac_address, ip_address=ip_address, clk_freq=clk_freq) self.add_csr("ethcore") if isinstance(platform.toolchain, XilinxVivadoToolchain): self.crg.cd_sys.clk.attr.add("keep") ethphy.crg.cd_eth_rx.clk.attr.add("keep") ethphy.crg.cd_eth_tx.clk.attr.add("keep") platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9 / 125e6) platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9 / 125e6) platform.add_false_path_constraints(self.crg.cd_sys.clk, ethphy.crg.cd_eth_rx.clk, ethphy.crg.cd_eth_tx.clk)
def __init__(self, *args, **kwargs): BaseSoC.__init__(self, *args, **kwargs) self.submodules.ethphy = LiteEthPHY( self.platform.request("eth_clocks"), self.platform.request("eth"), clk_freq=self.clk_freq) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def __init__(self, platform, clk_freq=166 * 1000000, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="LiteEth Base Design", with_timer=False) self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus) # ethernet PHY and UDP/IP stack self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq) self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq) if isinstance(platform.toolchain, XilinxVivadoToolchain): self.specials += [ Keep(self.crg.cd_sys.clk), Keep(self.phy.crg.cd_eth_rx.clk), Keep(self.phy.crg.cd_eth_tx.clk) ] platform.add_platform_command(""" create_clock -name sys_clk -period 6.0 [get_nets sys_clk] create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk] create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk] set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk] set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk] """)
def __init__(self, platform, mac_address=0x10e2d5000000, ip_address="192.168.1.50"): clk_freq = int(1e9 / platform.default_clk_period) SoCCore.__init__(self, platform, clk_freq, cpu_type=None, csr_data_width=32, with_uart=False, ident="Daisho USB3.0 Test Design", with_timer=False) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # uart <--> wishbone self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) # ethernet PHY and UDP/IP stack self.submodules.eth_phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq) self.submodules.eth_core = LiteEthUDPIPCore(self.eth_phy, mac_address, convert_ip(ip_address), clk_freq) # ethernet <--> wishbone self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.crg.cd_sys.clk.attr.add("keep") self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 6.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 8.0) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 8.0) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk)
def __init__(self, platform, with_ethernet=False, **kwargs): sys_clk_freq = int(1e9/platform.default_clk_period) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHY( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), clk_freq = self.clk_freq) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy)
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on KC705", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), clk_freq=self.clk_freq) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, **kwargs): HelloLtc.__init__(self, **kwargs) p = self.platform # ethernet PHY and UDP/IP stack mac_address = 0x01E625688D7C ip_address = "192.168.1.50" self.submodules.ethphy = LiteEthPHY( p.request("eth_clocks"), p.request("eth"), self.clk_freq, # avoid huge reset delay in simulation with_hw_init_reset="synth" in argv ) self.submodules.core = LiteEthUDPIPCore( self.ethphy, mac_address, convert_ip(ip_address), self.clk_freq ) # Etherbone = wishbone master = read and write registers remotely self.submodules.etherbone = LiteEthEtherbone( self.core.udp, 1234, mode="master" ) self.add_wb_master(self.etherbone.wishbone.bus)
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_pcie=False, with_sata=False, **kwargs): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on KC705", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), clk_freq=self.clk_freq) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_csr("pcie_phy") self.add_pcie(phy=self.pcie_phy, ndmas=1) # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # IOs _sata_io = [ # SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter ( "sfp2sata", 0, Subsignal("tx_p", Pins("H2")), Subsignal("tx_n", Pins("H1")), Subsignal("rx_p", Pins("G4")), Subsignal("rx_n", Pins("G3")), ), ] platform.add_extension(_sata_io) # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, refclk=sata_refclk, pads=platform.request("sfp2sata"), gen="gen2", clk_freq=sys_clk_freq, data_width=16) self.add_csr("sata_phy") # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, platform, connector="pcie", with_etherbone=True, with_analyzer=True): sys_clk_freq = int(125e6) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Serial Bridge ---------------------------------------------------------------------------- self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq) self.add_wb_master(self.bridge.wishbone) # Ethernet <--> Wishbone ------------------------------------------------------------------- if with_etherbone: # phy self.submodules.eth_phy = LiteEthPHY( clock_pads=platform.request("eth_clocks"), pads=platform.request("eth"), clk_freq=sys_clk_freq) self.add_csr("eth_phy") # core self.submodules.eth_core = LiteEthUDPIPCore( phy=self.eth_phy, mac_address=0x10e2d5000000, ip_address="192.168.1.50", clk_freq=sys_clk_freq) # etherbone self.submodules.etherbone = LiteEthEtherbone( self.eth_core.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9 / 125e6) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9 / 125e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.eth_phy.crg.cd_eth_rx.clk, self.eth_phy.crg.cd_eth_tx.clk) # USB3 SerDes ------------------------------------------------------------------------------ usb3_serdes = K7USB3SerDes(platform, sys_clk=self.crg.cd_sys.clk, sys_clk_freq=sys_clk_freq, refclk_pads=ClockSignal("clk125"), refclk_freq=125e6, tx_pads=platform.request(connector + "_tx"), rx_pads=platform.request(connector + "_rx")) self.submodules += usb3_serdes platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") # USB3 PIPE -------------------------------------------------------------------------------- usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq) self.submodules.usb3_pipe = usb3_pipe self.comb += usb3_pipe.reset.eq(platform.request("cpu_reset")) # USB3 Core -------------------------------------------------------------------------------- usb3_core = USB3Core(platform) self.submodules.usb3_core = usb3_core self.comb += [ usb3_pipe.source.connect(usb3_core.sink), usb3_core.source.connect(usb3_pipe.sink), usb3_core.reset.eq(~usb3_pipe.ready), ] self.add_csr("usb3_core") # Leds ------------------------------------------------------------------------------------- self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready) self.comb += platform.request("user_led", 1).eq(usb3_pipe.ready) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ # LFPS usb3_serdes.tx_idle, usb3_serdes.rx_idle, usb3_serdes.tx_pattern, usb3_serdes.rx_polarity, usb3_pipe.lfps.rx_polling, usb3_pipe.lfps.tx_polling, # Training Sequence usb3_pipe.ts.tx_enable, usb3_pipe.ts.rx_ts1, usb3_pipe.ts.rx_ts2, usb3_pipe.ts.tx_enable, usb3_pipe.ts.tx_tseq, usb3_pipe.ts.tx_ts1, usb3_pipe.ts.tx_ts2, usb3_pipe.ts.tx_done, # LTSSM usb3_pipe.ltssm.polling.fsm, usb3_pipe.ready, # Endpoints usb3_serdes.rx_datapath.skip_remover.skip, usb3_serdes.source, usb3_serdes.sink, usb3_pipe.source, usb3_pipe.sink, ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, 4096, csr_csv="tools/analyzer.csv") self.add_csr("analyzer")
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, cpu_variant="1c", **kwargs): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- kwargs["integrated_rom_size"] = 0x10000 SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_cls=VexRiscvSMP, cpu_variant=cpu_variant, **kwargs) # PLIC ------------------------------------------------------------------------------------ self.bus.add_slave("plic", self.cpu.plicbus, region=SoCRegion(origin=0xf0C00000, size=0x400000, cached=False)) # CLINT ------------------------------------------------------------------------------------ self.bus.add_slave("clint", self.cpu.cbus, region=SoCRegion(origin=0xf0010000, size=0x10000, cached=False)) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( pads=PHYPadsReducer(platform.request("ddram"), [1, 2]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, cmd_latency=1) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True, controller_settings=ControllerSettings( cmd_buffer_buffered=False, with_auto_precharge=False)) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), clk_freq=self.clk_freq) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # JTAG --------------------------------------------------------------------------------- self.submodules.jtag = S7JTAG() self.comb += self.cpu.jtag_clk.eq(self.jtag.tck) self.comb += self.cpu.jtag_enable.eq(1) self.comb += self.cpu.jtag_capture.eq(self.jtag.capture) self.comb += self.cpu.jtag_shift.eq(self.jtag.shift) self.comb += self.cpu.jtag_update.eq(self.jtag.update) self.comb += self.cpu.jtag_reset.eq(self.jtag.reset) self.comb += self.cpu.jtag_tdi.eq(self.jtag.tdi) self.comb += self.jtag.tdo.eq(self.cpu.jtag_tdo)
def __init__(self, platform, connector="sfp", with_etherbone=True, with_analyzer=True): sys_clk_freq = int(125e6) # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # UARTBone --------------------------------------------------------------------------------- self.add_uartbone() # Etherbone -------------------------------------------------------------------------------- if with_etherbone: self.submodules.eth_phy = LiteEthPHY( clock_pads=platform.request("eth_clocks"), pads=platform.request("eth"), clk_freq=sys_clk_freq) self.add_etherbone(phy=self.eth_phy, ip_address="192.168.1.50") # USB3 SerDes ------------------------------------------------------------------------------ usb3_serdes = K7USB3SerDes(platform, sys_clk=self.crg.cd_sys.clk, sys_clk_freq=sys_clk_freq, refclk_pads=ClockSignal("clk125"), refclk_freq=125e6, tx_pads=platform.request(connector + "_tx"), rx_pads=platform.request(connector + "_rx")) self.submodules += usb3_serdes platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") # USB3 PIPE -------------------------------------------------------------------------------- usb3_pipe = USB3PIPE(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq) self.submodules.usb3_pipe = usb3_pipe self.comb += usb3_pipe.reset.eq(platform.request("cpu_reset")) # USB3 Core -------------------------------------------------------------------------------- usb3_core = USB3Core(platform) self.submodules.usb3_core = usb3_core self.comb += [ usb3_pipe.source.connect(usb3_core.sink), usb3_core.source.connect(usb3_pipe.sink), usb3_core.reset.eq(~usb3_pipe.ready), ] # Debug IOs (Through CYUSB3ACC-005) -------------------------------------------------------- _debug_ios = [ ("tx_idle", 0, Pins("AK20"), IOStandard("LVCMOS12")), # I2C_SDA ("rx_idle", 0, Pins("AK21"), IOStandard("LVCMOS12")), # I2C_SCL ] self.platform.add_extension(_debug_ios) self.comb += [ platform.request("tx_idle").eq(usb3_serdes.tx_idle), platform.request("rx_idle").eq(usb3_serdes.rx_idle), ] # Leds ------------------------------------------------------------------------------------- self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready) self.comb += platform.request("user_led", 1).eq(usb3_pipe.ready) # Analyzer --------------------------------------------------------------------------------- if with_analyzer: analyzer_signals = [ # LFPS usb3_serdes.tx_idle, usb3_serdes.rx_idle, usb3_serdes.tx_pattern, usb3_serdes.rx_polarity, usb3_pipe.lfps.rx_polling, usb3_pipe.lfps.tx_polling, # Training Sequence usb3_pipe.ts.tx_enable, usb3_pipe.ts.rx_ts1, usb3_pipe.ts.rx_ts2, usb3_pipe.ts.tx_enable, usb3_pipe.ts.tx_tseq, usb3_pipe.ts.tx_ts1, usb3_pipe.ts.tx_ts2, usb3_pipe.ts.tx_done, # LTSSM usb3_pipe.ltssm.polling.fsm, usb3_pipe.ready, # Endpoints usb3_serdes.rx_datapath.skip_remover.skip, usb3_serdes.source, usb3_serdes.sink, usb3_pipe.source, usb3_pipe.sink, ] self.submodules.analyzer = LiteScopeAnalyzer( analyzer_signals, 4096, csr_csv="analyzer.csv")
def __init__(self, sys_clk_freq=int(150e6), with_ethernet=False, with_sata=False, **kwargs): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on KC705", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Ethernet --------------------------------------------------------------------------------- if with_ethernet: self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), clk_freq=self.clk_freq) self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) # SATA (Experimental) ---------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litex.soc.interconnect import wishbone from litesata.phy import LiteSATAPHY from litesata.core import LiteSATACore from litesata.frontend.arbitration import LiteSATACrossbar from litesata.frontend.dma import LiteSATABlock2MemDMA # IOs _sata_io = [ # SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter ( "sfp", 0, Subsignal("txp", Pins("H2")), Subsignal("txn", Pins("H1")), Subsignal("rxp", Pins("G4")), Subsignal("rxn", Pins("G3")), ), ] platform.add_extension(_sata_io) # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") # PHY self.submodules.sata_phy = LiteSATAPHY( platform.device, refclk=sata_refclk, pads=platform.request("sfp"), gen="gen1", clk_freq=sys_clk_freq, data_width=16) # Core self.submodules.sata_core = LiteSATACore(self.sata_phy) # Crossbar self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core) # Block2Mem DMA bus = wishbone.Interface(data_width=32, adr_width=32) self.submodules.sata_block2mem = LiteSATABlock2MemDMA( user_port=self.sata_crossbar.get_port(), bus=bus, endianness=self.cpu.endianness) self.bus.add_master("sata_block2mem", master=bus) self.add_csr("sata_block2mem") # Timing constraints platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9 / 75e6) platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9 / 75e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.sata_phy.crg.cd_sata_tx.clk, self.sata_phy.crg.cd_sata_tx.clk) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): platform = stlv7325.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on STLV7325", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq, ) self.add_sdram( "sdram", phy=self.ddrphy, module=MT8JTF12864(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192), ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks", 0), pads=self.platform.request("eth", 0), clk_freq=self.clk_freq) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width=128, bar0_size=0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) # TODO verify / test # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY # RefClk, Generate 150MHz from PLL. self.clock_domains.cd_sata_refclk = ClockDomain() self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) sata_refclk = ClockSignal("sata_refclk") platform.add_platform_command( "set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") # PHY self.submodules.sata_phy = LiteSATAPHY(platform.device, refclk=sata_refclk, pads=platform.request( "sata", 0), gen="gen2", clk_freq=sys_clk_freq, data_width=16) # Core self.add_sata(phy=self.sata_phy, mode="read+write") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led_n"), sys_clk_freq=sys_clk_freq) # I2C -------------------------------------------------------------------------------------- self.submodules.i2c = I2CMaster(platform.request("i2c"))
def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, video_timing="640x480@60Hz", **kwargs): platform = qmtech_wukong.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on QMTECH Wukong Board", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- with_video_pll = (with_video_terminal or with_video_framebuffer) self.submodules.crg = _CRG( platform, sys_clk_freq, with_video_pll=with_video_pll, pix_clk=video_timings[video_timing]["pix_clk"]) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K128M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHY( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth"), clk_freq=sys_clk_freq) if with_ethernet: self.add_ethernet(phy=self.ethphy, nrxslots=2) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoS7HDMIPHY( platform.request("hdmi_out"), clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings=video_timing, clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings=video_timing, clock_domain="hdmi")