def __init__(self, pads):
# Control
self.bitslip_value = bitslip_value = Signal(6)
# Status
self.idle = idle = Signal()
self.comma = comma = Signal()
# Datapath
self.source = source = stream.Endpoint([("data", 32)])
# # #
# Input data (on rising edge of sys_clk)
data = Signal()
data_d = Signal()
if hasattr(pads, "rx_p"):
self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data)
else:
self.comb += data.eq(pads.rx)
self.sync += data_d.eq(data)
# Datapath
self.submodules.datapath = datapath = RXDatapath(1)
self.comb += [
datapath.sink.valid.eq(1),
datapath.sink.data.eq(data_d),
datapath.bitslip_value.eq(bitslip_value),
datapath.source.connect(source),
idle.eq(datapath.idle),
comma.eq(datapath.comma)
]
def __init__(self, pads):
# Control
self.delay_rst = Signal()
self.delay_inc = Signal()
self.bitslip_value = bitslip_value = Signal(6)
# Status
self.idle = idle = Signal()
self.comma = comma = Signal()
# Datapath
self.source = source = stream.Endpoint([("data", 32)])
# # #
# Data input (DDR with sys4x)
data_nodelay = Signal()
data_delayed = Signal()
data_deserialized = Signal(8)
self.specials += [
DifferentialInput(pads.rx_p, pads.rx_n, data_nodelay),
Instance("IDELAYE3",
p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0,
p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
p_DELAY_FORMAT="COUNT", p_DELAY_SRC="IDATAIN",
p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=0,
i_CLK=ClockSignal("sys"),
i_RST=self.delay_rst, i_LOAD=0,
i_INC=1, i_EN_VTC=0,
i_CE=self.delay_inc,
i_IDATAIN=data_nodelay, o_DATAOUT=data_delayed
),
Instance("ISERDESE3",
p_IS_CLK_INVERTED=0,
p_IS_CLK_B_INVERTED=1,
p_DATA_WIDTH=8,
i_D=data_delayed,
i_RST=ResetSignal("sys"),
i_FIFO_RD_CLK=0, i_FIFO_RD_EN=0,
i_CLK=ClockSignal("sys4x"),
i_CLK_B=ClockSignal("sys4x"), # locally inverted
i_CLKDIV=ClockSignal("sys"),
o_Q=data_deserialized
)
]
# Datapath
self.submodules.datapath = datapath = RXDatapath(8)
self.comb += [
datapath.sink.valid.eq(1),
datapath.sink.data.eq(data_deserialized),
datapath.bitslip_value.eq(bitslip_value),
datapath.source.connect(source),
idle.eq(datapath.idle),
comma.eq(datapath.comma)
]
def __init__(self, pads):
# Control
self.delay_rst = Signal()
self.delay_inc = Signal()
self.shift = Signal()
# Status
self.idle = idle = Signal()
self.comma = comma = Signal()
# Datapath
self.source = source = stream.Endpoint([("data", 32)])
# # #
_shift = Signal(3)
self.sync += If(self.shift, _shift.eq(_shift + 1))
# Data input (DDR with sys4x)
data_nodelay = Signal()
data_delayed = Signal()
self.data = data = Signal(8)
self.specials += [
DifferentialInput(pads.rx_p, pads.rx_n, data_nodelay),
Instance(
"IDELAYE2",
p_DELAY_SRC="IDATAIN",
p_SIGNAL_PATTERN="DATA",
p_CINVCTRL_SEL="FALSE",
p_HIGH_PERFORMANCE_MODE="TRUE",
p_REFCLK_FREQUENCY=200.0,
p_PIPE_SEL="FALSE",
p_IDELAY_TYPE="VARIABLE",
p_IDELAY_VALUE=0,
i_C=ClockSignal(),
i_LD=self.delay_rst,
i_CE=self.delay_inc,
i_LDPIPEEN=0,
i_INC=1,
i_IDATAIN=data_nodelay,
o_DATAOUT=data_delayed,
),
Instance(
"ISERDESE2",
p_DATA_WIDTH=8,
p_DATA_RATE="DDR",
p_SERDES_MODE="MASTER",
p_INTERFACE_TYPE="NETWORKING",
p_NUM_CE=1,
p_IOBDELAY="IFD",
i_DDLY=data_delayed,
i_CE1=1,
i_RST=ResetSignal("sys"),
i_CLK=ClockSignal("sys4x"),
i_CLKB=~ClockSignal("sys4x"),
i_CLKDIV=ClockSignal("sys"),
i_BITSLIP=self.shift,
o_Q8=data[0],
o_Q7=data[1],
o_Q6=data[2],
o_Q5=data[3],
o_Q4=data[4],
o_Q3=data[5],
o_Q2=data[6],
o_Q1=data[7],
)
]
# Datapath
self.submodules.datapath = datapath = RXDatapath(8)
self.comb += [
datapath.sink.valid.eq(1),
datapath.sink.data.eq(data),
datapath.shift.eq(self.shift & (_shift == 0b111)),
datapath.source.connect(source),
idle.eq(datapath.idle),
comma.eq(datapath.comma)
]