def __init__(self, user_port, count_width=32): self.start = Signal() self.sector = Signal(48) self.count = Signal(16) self.random = Signal() self.done = Signal() self.aborted = Signal() self.errors = Signal(32) # Note: Not used for writes # # # n = user_port.dw // 32 count_mult = user_port.dw // user_port.controller_dw if count_mult == 0: raise ValueError source, sink = user_port.sink, user_port.source count = Signal(count_width) scrambler = ResetInserter()(Scrambler()) self.submodules += scrambler self.submodules.fsm = fsm = FSM(reset_state="IDLE") fsm.act("IDLE", self.done.eq(1), scrambler.reset.eq(1), NextValue(count, 0), If(self.start, NextState("SEND-CMD-AND-DATA"))) self.comb += [ source.last.eq(count == (logical_sector_size // 4 * self.count) - 1), source.write.eq(1), source.sector.eq(self.sector), source.count.eq(self.count * count_mult), If(self.random, source.data.eq(Replicate(scrambler.value, n))).Else( source.data.eq(Replicate(count, n))) ] fsm.act( "SEND-CMD-AND-DATA", source.valid.eq(1), If(source.valid & source.ready, scrambler.ce.eq(1), NextValue(count, count + 1), If(source.last, NextState("WAIT-ACK")))) fsm.act("WAIT-ACK", sink.ready.eq(1), If(sink.valid, NextState("IDLE"))) self.sync += [ If(self.start, self.aborted.eq(0)).Elif( sink.valid & sink.ready, self.aborted.eq(self.aborted | sink.failed)) ]
def __init__(self, user_port, counter_width=32): self.start = Signal() self.sector = Signal(48) self.count = Signal(16) self.random = Signal() self.done = Signal() self.aborted = Signal() self.errors = Signal(counter_width) # # # n = user_port.dw//32 count_mult = user_port.dw//user_port.controller_dw if count_mult == 0: raise ValueError source, sink = user_port.sink, user_port.source counter = Signal(counter_width) counter_ce = Signal() counter_reset = Signal() self.sync += \ If(counter_reset, counter.eq(0) ).Elif(counter_ce, counter.eq(counter + 1) ) error_counter = Signal(counter_width) error_counter_ce = Signal() error_counter_reset = Signal() self.sync += \ If(error_counter_reset, error_counter.eq(0) ).Elif(error_counter_ce, error_counter.eq(error_counter + 1) ) self.comb += self.errors.eq(error_counter) scrambler = ResetInserter()(Scrambler()) self.submodules += scrambler self.comb += [ scrambler.reset.eq(counter_reset), scrambler.ce.eq(counter_ce) ] self.fsm = fsm = FSM(reset_state="IDLE") self.submodules += self.fsm fsm.act("IDLE", self.done.eq(1), counter_reset.eq(1), If(self.start, error_counter_reset.eq(1), NextState("SEND_CMD") ) ) self.comb += [ source.last.eq(1), source.read.eq(1), source.sector.eq(self.sector), source.count.eq(self.count*count_mult), ] fsm.act("SEND_CMD", source.valid.eq(1), If(source.ready, counter_reset.eq(1), NextState("WAIT_ACK") ) ) fsm.act("WAIT_ACK", If(sink.valid & sink.read, NextState("RECEIVE_DATA") ) ) expected_data = Signal(n*32) self.comb += \ If(self.random, expected_data.eq(Replicate(scrambler.value, n)) ).Else( expected_data.eq(Replicate(counter, n)) ) fsm.act("RECEIVE_DATA", sink.ready.eq(1), If(sink.valid, counter_ce.eq(1), If(sink.data != expected_data, error_counter_ce.eq(~sink.end) ), If(sink.end, If(sink.last, NextState("IDLE") ).Else( NextState("WAIT_ACK") ) ) ) ) self.sync += \ If(self.start, self.aborted.eq(0) ).Elif(sink.valid & sink.ready, self.aborted.eq(self.aborted | sink.failed) )
def __init__(self, length): self.submodules.scrambler = ResetInserter()(Scrambler()) self.length = length