def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="radiant", help="FPGA toolchain: radiant (default) or prjoxide")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
parser.add_argument("--serial", default="serial", help="UART Pins: serial (default, requires R15 and R17 to be soldered) or serial_pmod[0-2]")
parser.add_argument("--prog-target", default="direct", help="Programming Target: direct or flash")
builder_args(parser)
soc_core_args(parser)
oxide_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.prog_target)
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on Crosslink-NX VIP Board")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain",
default="radiant",
help="FPGA toolchain: radiant (default) or prjoxide")
parser.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency (default: 75MHz)")
parser.add_argument(
"--with-hyperram",
default="none",
help="Enable use of HyperRAM chip: none (default), 0 or 1")
parser.add_argument("--prog-target",
default="direct",
help="Programming Target: direct (default) or flash")
builder_args(parser)
soc_core_args(parser)
oxide_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
hyperram=args.with_hyperram,
toolchain=args.toolchain,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.prog_target)
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip (none, 0 or 1).")
target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
builder_args(parser)
soc_core_args(parser)
oxide_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
hyperram = args.with_hyperram,
toolchain = args.toolchain,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.prog_target)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on Crosslink-NX Eval Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--toolchain",
default="radiant",
help="FPGA toolchain (radiant or prjoxide).")
target_group.add_argument(
"--device",
default="LIFCL-40-9BG400C",
help="FPGA device (LIFCL-40-9BG400C or LIFCL-40-8BG400CES).")
target_group.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency.")
target_group.add_argument(
"--serial",
default="serial",
help=
"UART Pins (serial (requires R15 and R17 to be soldered) or serial_pmod[0-2])."
)
target_group.add_argument("--prog-target",
default="direct",
help="Programming Target (direct or flash).")
builder_args(parser)
soc_core_args(parser)
oxide_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
device=args.device,
toolchain=args.toolchain,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.prog_target)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
patch_cpu_variant()
parser = argparse.ArgumentParser(description="HPS SoC")
hps_soc_args(parser)
parser.add_argument("--debug",
action="store_true",
help="Enable debug mode")
parser.add_argument(
"--slim_cpu",
action="store_true",
help=
"DEPRECATED: use '--cpu-variant=slim+cfu' instead (Use slimmer VexRiscv (required for mnv2_first))"
)
parser.add_argument(
"--build",
action="store_true",
help="Whether to do a full build, including the bitstream")
parser.add_argument(
"--toolchain",
default="oxide",
help="Which toolchain to use: oxide (default) or radiant")
parser.add_argument(
"--parallel-nextpnr",
action="store_true",
help=
"Whether to use the parallel nextpnr script with the oxide toolchain")
parser.add_argument("--extra-nextpnr-params",
action="store_true",
help="Enable extra nextpnr parameters")
parser.add_argument(
"--synth_mode",
default="radiant",
help="Which synthesis mode to use with Radiant toolchain: "
"radiant/synplify (default), lse, or yosys")
parser.add_argument("--cpu-cfu",
default=None,
help="Specify file containing CFU Verilog module")
parser.add_argument("--cpu-variant",
default=None,
help="Which CPU variant to use")
parser.add_argument("--separate-arena",
action="store_true",
help="Create separate RAM for tensor arena")
parser.add_argument("--cfu-mport",
action="store_true",
help="Create a direct connection between CFU and LRAM")
parser.add_argument(
"--execute-from-lram",
action="store_true",
help=
"Make the CPU execute from integrated ROM stored in LRAM instead of flash"
)
parser.add_argument(
"--integrated-rom-init",
metavar="FILE",
help="Use FILE as integrated ROM data instead of default BIOS")
parser.add_argument("--build-bios",
action="store_true",
help="Flag to specify that the BIOS is built as well")
parser.add_argument("--just-synth",
action='store_true',
help="Stop after synthesis")
parser.add_argument(
"--dynamic-clock-control",
action="store_true",
help=
"Enable dynamic clock control between CPU and CFU to reduce FPGA power consumption."
)
args = parser.parse_args()
if args.integrated_rom_init:
integrated_rom_init = get_mem_data(args.integrated_rom_init, "little")
else:
integrated_rom_init = []
if args.cpu_variant:
variant = args.cpu_variant
elif args.cpu_cfu:
if args.slim_cpu:
variant = "slim+cfu+debug" if args.debug else "slim+cfu"
else:
variant = "full+cfu+debug" if args.debug else "full+cfu"
else:
variant = "full+debug" if args.debug else "full"
copy_cpu_variant_if_needed(variant)
soc = HpsSoC(Platform(args.toolchain, args.parallel_nextpnr,
args.extra_nextpnr_params, args.just_synth),
debug=args.debug,
variant=variant,
cpu_cfu=args.cpu_cfu,
execute_from_lram=args.execute_from_lram,
separate_arena=args.separate_arena,
integrated_rom_init=integrated_rom_init,
build_bios=args.build_bios,
cfu_mport=args.cfu_mport,
dynamic_clock_control=args.dynamic_clock_control)
if not args.build_bios:
# To still allow building libraries needed
# by the HPS software, without the necessity of
# having the BIOS (and its gatware requirements such as the Timer)
# this flag needs to be set to True
soc.integrated_rom_initialized = True
builder = create_builder(soc, args)
builder_kwargs = {}
if args.toolchain == "radiant":
builder_kwargs.update(radiant_build_argdict(args))
elif args.toolchain == "oxide":
builder_kwargs.update(oxide_argdict(args))
vns = builder.build(**builder_kwargs, run=args.build)
soc.do_exit(vns)
if not args.build:
print("Use --build to build the bitstream, if needed")