def main():
parser = argparse.ArgumentParser(description="do the thing")
#parser.add_argument("--load", action="store_true", help="load bitstream")
parser.add_argument("--flash", action="store_true", help="flash bitstream")
parser.add_argument("--sim", action="store_true", help="simulate")
parser.add_argument("--threads", default=1, help="simulate")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
build_kwargs = {}
if args.sim:
build_kwargs["threads"] = args.threads
build_kwargs["sim_config"] = sim_config
build_kwargs["opt_level"] = args.opt_level
build_kwargs["trace"] = args.trace
build_kwargs["trace_start"] = int(args.trace_start)
build_kwargs["trace_end"] = int(args.trace_end)
soc = N64SoC(
simulate=args.sim,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, "little"),
)
builder = Builder(soc, output_dir="build", csr_csv="scripts/csr.csv")
builder.build(run=not (args.sim or args.flash), **build_kwargs)
if args.flash:
from litex.build.lattice.programmer import IceStormProgrammer
prog = IceStormProgrammer()
#prog.flash(4194304, "sm64_swapped_half.n64")
prog.flash(bios_flash_offset, "build/software/bios/bios.bin")
prog.flash(0x00000000, "build/gateware/litex_platform_n64.bin")
if args.sim:
builder.build(build=False, **build_kwargs)