def main():
run_simulation(TB(), ncycles=8000, vcd_name="my.vcd", keep_files=True)
def gen_simulation(self, selfp):
# init CRC
selfp.scrambler.ce = 1
selfp.scrambler.reset = 1
yield
selfp.scrambler.reset = 0
# log results
yield
sim_values = []
for i in range(self.length):
sim_values.append(selfp.scrambler.value)
yield
# stop
selfp.scrambler.ce = 0
for i in range(32):
yield
# get C code reference
c_values = self.get_c_values(self.length)
# check results
s, l, e = check(c_values, sim_values)
print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__":
from litex.gen.sim.generic import run_simulation
length = 8192
run_simulation(TB(length), ncycles=length+100, vcd_name="my.vcd")
def main():
run_simulation(TB(), ncycles=8000, vcd_name="my.vcd", keep_files=True)
self.comb += [lfsr.ce.eq(self._dma.data.stb), self._dma.data.ack.eq(1)]
err_cnt = self._error_count.status
self.sync += [
If(self._reset.re, err_cnt.eq(0)).Elif(
self._dma.data.stb,
If(self._dma.data.d != lfsr.o, err_cnt.eq(err_cnt + 1)))
]
def get_csrs(self):
return [self._magic, self._reset, self._error_count
] + self._dma.get_csrs()
class _LFSRTB(Module):
def __init__(self, *args, **kwargs):
self.submodules.dut = LFSR(*args, **kwargs)
self.comb += self.dut.ce.eq(1)
def do_simulation(self, selfp):
print("{0:032x}".format(selfp.dut.o))
if __name__ == "__main__":
from litex.gen.fhdl import verilog
from litex.gen.sim.generic import run_simulation
lfsr = LFSR(3, 4, [3, 2])
print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o}))
run_simulation(_LFSRTB(128), ncycles=20)
