def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SC.SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(9)])
self.submodules.leds = Led(user_leds)
# Spi
self.submodules.spi = SPIMaster(platform.request("spi_master"))
# control_lcd
control_lcd = Cat(
*[platform.request("control_lcd", i) for i in range(3)])
self.submodules.ctrllcd = gpio.GPIOOut(control_lcd)
self.submodules.i2s = I2S(platform.request("i2s_"))
def __init__(self):
platform = nexys4ddr.Platform()
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="picorv32",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(16)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(16)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*
[platform.request("btn%c" % c) for c in ['c', 'd', 'u', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# RGB leds
SoCCore.add_csr(self, "led16")
self.submodules.led16 = rgbled.RGBLed(platform.request("led", 16))
SoCCore.add_csr(self, "led17")
self.submodules.led17 = rgbled.RGBLed(platform.request("led", 17))
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# Joystick SPI
SoCCore.add_csr(self, "joystick")
self.submodules.joystick = spijoystick.SpiJoystick(
platform.request("joystick"))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = cyc1000.Platform()
SoCSDRAM.__init__(
self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
# integrated_main_ram_size=0x4000,
**kwargs)
self.submodules.crg = _CRG(platform)
# self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7)))
# self.add_csr("leds", allow_user_defined=True)
# self.submodules.leds = ClassicLed(platform.request("user_led", 0))
self.add_csr("gpio_leds", allow_user_defined=True)
self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
# use micron device as winbond and ISSI not available
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, device, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = max1000.Platform(device)
# SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
# integrated_rom_size=0x8000,
# **kwargs)
# csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
SoCSDRAM.__init__(
self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x6000,
# integrated_main_ram_size=0x4000,
**kwargs)
self.mem_map['spiflash'] = 0x20000000
spiflash_pads = platform.request('spiflash')
self.add_memory_region("spiflash", self.mem_map["spiflash"],
8 * 1024 * 1024)
self.submodules.spiflash = SpiFlash(spiflash_pads,
dummy=8,
div=4,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
#self.spiflash.add_clk_primitive("xc7");
# 8 MB flash: W74M64FVSSIQ
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map['spiflash'])
# spi_flash.py supports max 16MB linear space
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.submodules.crg = _CRG(platform)
# self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7)))
self.add_csr("leds", allow_user_defined=True)
self.submodules.leds = ClassicLed(platform.request("user_led", 0))
# self.add_csr("gpio_leds", allow_user_defined=True)
self.add_csr("gpio_leds", allow_user_defined=True)
self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
# use micron device as winbond and ISSI not available
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self):
platform = tarjeta.Platform()
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x6000,
integrated_main_ram_size=2 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
SoCCore.add_csr(self, "ledRGB_1")
self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1))
SoCCore.add_csr(self, "ledRGB_2")
self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
def main():
platform = arcticserdes.Platform()
sys_clk_freq = 1/platform.default_clk_period*1e9
soc = soc_core.SoCCore(platform,
sys_clk_freq,
cpu_variant="lite",
integrated_rom_size=0x8000,
integrated_sram_size=0x8000)
user_led_n_pad = platform.request("user_led_n")
user_led = Signal()
soc.comb += user_led_n_pad.eq(~user_led)
soc.submodules.user_led = gpio.GPIOOut(user_led)
soc.add_csr("user_led")
builder = Builder(soc)
builder.build()
def __init__(self, platform, cpu, sim: bool, **kwargs):
sys_clk_freq = int(1e9 / platform.default_clk_period)
kwargs['with_uart'] = not sim
SoCCore.__init__(self, platform,
cpu_type=cpu.name,
clk_freq=sys_clk_freq,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
self.submodules.gpio_led = gpio.GPIOOut(platform.request("user_led"))
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map['main_ram'])
if sim:
# Serial -----------------------------------------------------------------------------------
self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy,
tx_fifo_depth=kwargs["uart_fifo_depth"],
rx_fifo_depth=kwargs["uart_fifo_depth"])
self.add_csr("uart")
self.add_interrupt("uart")
def __init__(self):
platform = tarjeta.Platform()
## add source verilog
platform.add_source("module/verilog/camara.v")
platform.add_source("module/verilog/Infrarrojo/modulo_ir.v")
platform.add_source("module/verilog/PWM/BloquePWM.v")
platform.add_source("module/verilog/PWM/PWM.v")
platform.add_source("module/verilog/PWM/MaquinaEstadosPWM.v")
platform.add_source("module/verilog/PWM/DivFreqPWM.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/bloqueultrasonido.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/contador.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/divisor.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrec.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecd.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecgen.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/divisorfrecme.v")
platform.add_source("module/verilog/Ultrasonido(NexysA7)/genpulsos.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/maquinadeestados.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/meultrasonido.v")
platform.add_source(
"module/verilog/Ultrasonido(NexysA7)/ultrasonido.v")
clk_freq = 100e6
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
SoCCore.add_csr(self, "ledRGB_1")
self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1))
SoCCore.add_csr(self, "ledRGB_2")
self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
#camara
"""
/* SoCCore.add_csr(self,"camara_cntrl")
SoCCore.add_interrupt(self,"camara_cntrl")
cam_data_in = Cat(*[platform.request("cam_data_in", i) for i in range(8)])
self.submodules.camara_cntrl = camara.Camara(platform.request("cam_xclk"),platform.request("cam_pclk"),cam_data_in)
"""
#serialA
from litex.soc.cores import uart
self.submodules.uart1_phy = uart.UARTPHY(
pads=platform.request("uart1"),
clk_freq=self.sys_clk_freq,
baudrate=9600)
self.submodules.uart1 = ResetInserter()(uart.UART(self.uart1_phy,
tx_fifo_depth=16,
rx_fifo_depth=16))
self.csr.add("uart1_phy", use_loc_if_exists=True)
self.csr.add("uart1", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"):
self.irq.add("uart1", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")
#Infrarrojo
SoCCore.add_csr(self, "infrarrojo_cntrl")
self.submodules.infrarrojo_cntrl = infrarrojo.Infrarrojo(
platform.request("ir_inout"))
#PWM
SoCCore.add_csr(self, "pwm_cntrl")
self.submodules.pwm_cntrl = pwm.PWM(platform.request("pwm_out"))
#Ultrasonido
SoCCore.add_csr(self, "ultrasonido")
self.submodules.ultrasonido = ultrasonido.Ultrasonido(
platform.request("us_trigger"), platform.request("us_echo"))
def __init__(self, platform, is_sim=False, debug=True, **kwargs):
clk_freq = int(12e6)
SoCCore.__init__(self,
platform,
clk_freq,
integrated_rom_size=16384,
integrated_sram_size=131072,
with_uart=True,
uart_stub=True,
**kwargs)
if is_sim:
self.submodules.crg = CocotbPlatform._CRG(self.platform)
else:
self.submodules.crg = _CRG(self.platform, fast_sysclk=False)
# Add a "Version" module so we can see what version of the board this is.
self.submodules.version = Version(
"proto2", [(0x02, "proto2", "Prototype Version 2 (red)")], 0)
# Add a "USB" module to let us debug the device.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.submodules.usb = ClockDomainsRenamer({
"usb_48": "clk48",
"usb_12": "clk12",
# })(DummyUsb(usb_iobuf, debug=debug, product="Hackaday Supercon Badge", cdc=True))
})(TriEndpointInterface(usb_iobuf, debug=debug))
dir_path = os.path.dirname(os.path.realpath(__file__))
if debug:
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(
platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
self.add_wb_master(self.usb.debug_bridge.wishbone)
if self.cpu_type is not None:
self.register_mem("vexriscv_debug", 0xf00f0000,
self.cpu.debug_bus, 0x200)
self.cpu.use_external_variant(dir_path +
"/rtl/VexRiscv_HaD_Debug.v")
elif self.cpu_type is not None:
self.cpu.use_external_variant(dir_path + "/rtl/VexRiscv_HaD.v")
# Add the 16 MB SPI flash as XIP memory at address 0x03000000
if not is_sim:
flash = SpiFlashDualQuad(platform.request("spiflash4x"),
dummy=6,
endianness="little")
flash.add_clk_primitive(self.platform.device)
self.submodules.lxspi = flash
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.lxspi.bus,
size=16 * 1024 * 1024)
# self.submodules.picorvspi = flash = PicoRVSpi(self.platform, pads=platform.request("spiflash"), size=16 * 1024 * 1024)
# self.register_mem("spiflash", self.mem_map["spiflash"], self.picorvspi.bus, size=self.picorvspi.size)
self.add_constant("ROM_BOOT_ADDRESS",
self.mem_map["spiflash"] + 0x300000)
# # Add the 16 MB SPI RAM at address 0x40000000 # Value at 40010000: afbfcfef
reset_cycles = 2**14 - 1
if is_sim:
reset_cycles = 0
ram = SpiRamDualQuad(platform.request("spiram4x", 0),
platform.request("spiram4x", 1),
dummy=5,
reset_cycles=reset_cycles,
qpi=True)
self.submodules.ram = ram
self.register_mem("main_ram",
self.mem_map["main_ram"],
self.ram.bus,
size=16 * 1024 * 1024)
# Let us reboot the device
self.submodules.reboot = Reboot(platform.request("programn"))
# Add a Messible for sending messages to the host
self.submodules.messible = Messible()
# Add an LCD so we can see what's up
self.submodules.lcdif = LCDIF(platform.request("lcd"))
# Ensure timing is correctly set up
if not is_sim:
self.platform.toolchain.build_template[
1] += " --speed 8" # Add "speed grade 8" to nextpnr-ecp5
self.platform.toolchain.freq_constraints["sys"] = 48
if is_sim:
self.add_wb_master(self.platform.request("wishbone"))
# SAO
if not kwargs["sao0_disable"]:
self.submodules.sao0 = ShittyAddOn(
self.platform,
self.platform.request("sao", 0),
disable_i2c=kwargs["sao0_disable_i2c"])
self.add_csr("sao0")
if not kwargs["sao1_disable"]:
self.submodules.sao1 = ShittyAddOn(
self.platform,
self.platform.request("sao", 1),
disable_i2c=kwargs["sao1_disable_i2c"])
self.add_csr("sao1")
# PMOD
platform.add_extension(_pmod_gpio)
self.submodules.pmod = GPIOBidirectional(
self.platform.request("pmod_gpio"))
self.add_csr("pmod")
# GENIO
if not kwargs["genio_disable"]:
platform.add_extension(_genio_gpio)
self.submodules.genio = GPIOBidirectional(
self.platform.request("genio_gpio"))
self.add_csr("genio")
# LEDs
self.submodules.led0 = gpio.GPIOOut(self.platform.request("led", 0))
self.add_csr("led0")
self.submodules.led1 = gpio.GPIOOut(self.platform.request("led", 1))
self.add_csr("led1")
# Keypad
self.submodules.keypad = gpio.GPIOIn(
Cat(self.platform.request("keypad", 0).flatten()))
self.add_csr("keypad")
def __init__(self):
platform = tarjeta.Platform()
## add source verilog
# camara.v
platform.add_source("module/verilog/camara/camara.v")
platform.add_source("module/verilog/camara/buffer_ram_dp.v")
platform.add_source("module/verilog/camara/cam_read.v")
platform.add_source("module/verilog/camara/procesamiento.v")
platform.add_source("module/verilog/camara/VGA_driver.v")
platform.add_source("module/verilog/camara/PLL/clk24_25_nexys4.v")
platform.add_source("module/verilog/camara/PLL/clk24_25_nexys4_0.v")
platform.add_source(
"module/verilog/camara/PLL/clk24_25_nexys4_clk_wiz.v")
# Radar
platform.add_source("module/verilog/radar/radar.v")
platform.add_source("module/verilog/radar/servo.v")
platform.add_source("module/verilog/radar/ultrasonido1.v")
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=10 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
#SoCCore.add_csr(self,"ledRGB_1")
#self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB",1))
#SoCCore.add_csr(self,"ledRGB_2")
#self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB",2))
# VGA
#SoCCore.add_csr(self,"vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i)
for i in range(4)]) # Se concatena
vsync = platform.request("vsync")
hsync = platform.request("hsync")
#self.submodules.vga_cntrl = vgacontroller.VGAcontroller(hsync,vsync, vga_red, vga_green, vga_blue)
#camara
SoCCore.add_csr(self, "camara_cntrl") # Incluir mapa de memoria
SoCCore.add_interrupt(self, "camara_cntrl")
cam_data_in = Cat(
*[platform.request("cam_data_in", i) for i in range(8)])
self.submodules.camara_cntrl = camara.Camara(
vsync, hsync, vga_red, vga_green, vga_blue,
platform.request("cam_xclk"), platform.request("cam_pwdn"),
platform.request("cam_pclk"), cam_data_in,
platform.request("cam_vsync"), platform.request("cam_href"))
# radar
SoCCore.add_csr(self, "radar_cntrl") # Incluir mapa de memoria
self.submodules.radar_cntrl = radar.Radar(platform.request("echo"),
platform.request("done"),
platform.request("trigger"),
platform.request("PWM"))
def __init__(self):
platform = tarjeta.Platform()
## add source verilog
platform.add_source("module/verilog/camara.v")
clk_freq = 100e6
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type="picorv32",
# cpu_type="vexriscv",
clk_freq=100e6,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk"),
~platform.request("cpu_reset"))
# Leds
SoCCore.add_csr(self, "leds")
user_leds = Cat(*[platform.request("led", i) for i in range(10)])
self.submodules.leds = gpio.GPIOOut(user_leds)
# Switchs
SoCCore.add_csr(self, "switchs")
user_switchs = Cat(*[platform.request("sw", i) for i in range(8)])
self.submodules.switchs = gpio.GPIOIn(user_switchs)
# Buttons
SoCCore.add_csr(self, "buttons")
user_buttons = Cat(
*[platform.request("btn%c" % c) for c in ['c', 'r', 'l']])
self.submodules.buttons = gpio.GPIOIn(user_buttons)
# 7segments Display
SoCCore.add_csr(self, "display")
display_segments = Cat(
*[platform.request("display_segment", i) for i in range(8)])
display_digits = Cat(
*[platform.request("display_digit", i) for i in range(8)])
self.submodules.display = sevensegment.SevenSegment(
display_segments, display_digits)
# RGB leds
SoCCore.add_csr(self, "ledRGB_1")
self.submodules.ledRGB_1 = rgbled.RGBLed(platform.request("ledRGB", 1))
SoCCore.add_csr(self, "ledRGB_2")
self.submodules.ledRGB_2 = rgbled.RGBLed(platform.request("ledRGB", 2))
# VGA
SoCCore.add_csr(self, "vga_cntrl")
vga_red = Cat(*[platform.request("vga_red", i) for i in range(4)])
vga_green = Cat(*[platform.request("vga_green", i) for i in range(4)])
vga_blue = Cat(*[platform.request("vga_blue", i) for i in range(4)])
self.submodules.vga_cntrl = vgacontroller.VGAcontroller(
platform.request("hsync"), platform.request("vsync"), vga_red,
vga_green, vga_blue)
#camara
SoCCore.add_csr(self, "camara_cntrl")
SoCCore.add_interrupt(self, "camara_cntrl")
cam_data_in = Cat(
*[platform.request("cam_data_in", i) for i in range(8)])
self.submodules.camara_cntrl = camara.Camara(
platform.request("cam_xclk"), platform.request("cam_pclk"),
cam_data_in)
#serialA
from litex.soc.cores import uart
self.submodules.uart1_phy = uart.UARTPHY(
pads=platform.request("uart1"),
clk_freq=self.sys_clk_freq,
baudrate=115200)
self.submodules.uart1 = ResetInserter()(uart.UART(self.uart1_phy,
tx_fifo_depth=16,
rx_fifo_depth=16))
self.csr.add("uart1_phy", use_loc_if_exists=True)
self.csr.add("uart1", use_loc_if_exists=True)
if hasattr(self.cpu, "interrupt"):
self.irq.add("uart1", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=100e6,
ident="LiteX CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
self.submodules.trigger = gpio.GPIOOut(platform.request("pmodUS_trig"))
self.add_csr("trigger")
self.submodules.echo = gpio.GPIOIn(platform.request("pmodUS_echo"))
self.add_csr("echo")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width=32,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, D0_D8, CS, RS, RD, WR):
self.D0_D8 = gpio.GPIOOut(Signal(8))
self.CS = gpio.GPIOOut(Signal())
self.RS = gpio.GPIOOut(Signal())
self.RD = gpio.GPIOOut(Signal())
self.WR = gpio.GPIOOut(Signal())