Пример #1
0
    def __init__(self,
                 sys_clk_freq=int(100e6),
                 with_led_chaser=True,
                 with_pcie=False,
                 **kwargs):
        platform = tagus.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Tagus",
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
                platform.request("ddram"),
                memtype="DDR3",
                nphases=4,
                sys_clk_freq=sys_clk_freq,
                iodelay_clk_freq=200e6)
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=MT41J128M16(sys_clk_freq, "1:4"),
                           size=0x40000000,
                           l2_cache_size=kwargs.get("l2_size", 8192))

        # PCIe -------------------------------------------------------------------------------------
        if with_pcie:
            self.submodules.pcie_phy = S7PCIEPHY(platform,
                                                 platform.request("pcie_x1"),
                                                 data_width=64,
                                                 bar0_size=0x20000)
            self.add_pcie(phy=self.pcie_phy, ndmas=1)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads=platform.request_all("user_led"),
                sys_clk_freq=sys_clk_freq)
Пример #2
0
    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
        platform = mimas_a7.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Mimas A7",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
                platform.request("ddram"),
                memtype="DDR3",
                nphases=4,
                sys_clk_freq=sys_clk_freq)
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=MT41J128M16(sys_clk_freq, "1:4"),
                           origin=self.mem_map["main_ram"],
                           size=kwargs.get("max_sdram_size", 0x40000000),
                           l2_cache_size=kwargs.get("l2_size", 8192),
                           l2_cache_min_data_width=kwargs.get(
                               "min_l2_data_width", 128),
                           l2_cache_reverse=True)

        # Ethernet ---------------------------------------------------------------------------------
        if with_ethernet:
            self.submodules.ethphy = LiteEthPHYRGMII(
                clock_pads=self.platform.request("eth_clocks"),
                pads=self.platform.request("eth"))
            self.add_csr("ethphy")
            self.add_ethernet(phy=self.ethphy)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
        self.add_csr("leds")
Пример #3
0
    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
        platform = kc705.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on KC705",
            ident_version  = True,
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                memtype      = "DDR3",
                nphases      = 4,
                sys_clk_freq = sys_clk_freq,
                cmd_latency  = 1)
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                phy                     = self.ddrphy,
                module                  = MT8JTF12864(sys_clk_freq, "1:4"),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )

        # Ethernet ---------------------------------------------------------------------------------
        if with_ethernet:
            self.submodules.ethphy = LiteEthPHY(
                clock_pads = self.platform.request("eth_clocks"),
                pads       = self.platform.request("eth"),
                clk_freq   = self.clk_freq)
            self.add_csr("ethphy")
            self.add_ethernet(phy=self.ethphy)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")
Пример #4
0
    def __init__(self, sys_clk_freq=int(50e6), with_mister_sdram=True, with_mister_vga=False, sdram_rate="1:1", **kwargs):
        platform = de10nano.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on DE10-Nano",
            ident_version  = True,
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram, sdram_rate=sdram_rate)

        # SDR SDRAM --------------------------------------------------------------------------------
        if with_mister_sdram and not self.integrated_main_ram_size:
            sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
            self.add_sdram("sdram",
                phy                     = self.sdrphy,
                module                  = AS4C32M16(sys_clk_freq, sdram_rate),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )

        # VGA terminal -----------------------------------------------------------------------------
        if with_mister_vga:
            self.submodules.terminal = terminal = Terminal()
            self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
            vga_pads = platform.request("vga")
            self.comb += [
                vga_pads.vsync.eq(terminal.vsync),
                vga_pads.hsync.eq(terminal.hsync),
                vga_pads.red.eq(terminal.red[2:8]),
                vga_pads.green.eq(terminal.green[2:8]),
                vga_pads.blue.eq(terminal.blue[2:8])
            ]

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = platform.request_all("user_led"),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")
Пример #5
0
    def __init__(self, bios_flash_offset, sys_clk_freq=int(50e6), **kwargs):
        platform = beaglewire.Platform()

        # Disable Integrated ROM since too large for iCE40.
        kwargs["integrated_rom_size"] = 0
        kwargs["integrated_sram_size"] = 2 * kB

        # Set CPU reset address
        kwargs[
            "cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Beaglewire",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # SDR SDRAM --------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
                                               sys_clk_freq)
            self.add_sdram("sdram",
                           phy=self.sdrphy,
                           module=MT48LC32M8(sys_clk_freq, "1:1"),
                           l2_cache_size=kwargs.get("l2_size", 1024))

        # SPI Flash --------------------------------------------------------------------------------
        self.add_spi_flash(mode="1x", dummy_cycles=8)

        # Add ROM linker region --------------------------------------------------------------------
        self.bus.add_region(
            "rom",
            SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset,
                      size=32 * kB,
                      linker=True))

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
Пример #6
0
    def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, **kwargs):
        platform = c10lprefkit.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on C10 LP RefKit",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # HyperRam ---------------------------------------------------------------------------------
        self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
        self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
        self.add_memory_region("hyperram", self.mem_map["hyperram"],
                               8 * 1024 * 1024)

        # SDR SDRAM --------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
                                               sys_clk_freq)
            self.add_sdram("sdram",
                           phy=self.sdrphy,
                           module=MT48LC16M16(sys_clk_freq, "1:1"),
                           origin=self.mem_map["main_ram"],
                           size=kwargs.get("max_sdram_size", 0x40000000),
                           l2_cache_size=kwargs.get("l2_size", 8192),
                           l2_cache_min_data_width=kwargs.get(
                               "min_l2_data_width", 128),
                           l2_cache_reverse=True)

        # Ethernet ---------------------------------------------------------------------------------
        if with_ethernet:
            self.submodules.ethphy = LiteEthPHYMII(
                clock_pads=self.platform.request("eth_clocks"),
                pads=self.platform.request("eth"))
            self.add_ethernet(phy=self.ethphy)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
    def __init__(self, **kwargs):
        sys_clk_freq = (83 + Fraction(1, 3)) * 1000 * 1000
        platform = pipistrello.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Pipistrello",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)
        self.platform.add_period_constraint(self.crg.cd_sys.clk,
                                            1e9 / sys_clk_freq)

        # LPDDR SDRAM ------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
                platform.request("ddram"),
                memtype="LPDDR",
                rd_bitslip=1,
                wr_bitslip=3,
                dqs_ddr_alignment="C1")
            self.comb += [
                self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
                self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
            ]
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=MT46H32M16(sys_clk_freq, "1:2"),
                           origin=self.mem_map["main_ram"],
                           size=kwargs.get("max_sdram_size", 0x40000000),
                           l2_cache_size=kwargs.get("l2_size", 8192),
                           l2_cache_min_data_width=kwargs.get(
                               "min_l2_data_width", 128),
                           l2_cache_reverse=True)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
        self.add_csr("leds")
Пример #8
0
    def __init__(self,
                 variant="s7-50",
                 sys_clk_freq=int(100e6),
                 with_spi_flash=False,
                 with_led_chaser=True,
                 **kwargs):
        platform = arty_s7.Platform(variant=variant)

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Arty S7",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
                platform.request("ddram"),
                memtype="DDR3",
                nphases=4,
                sys_clk_freq=sys_clk_freq)
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=MT41K128M16(sys_clk_freq, "1:4"),
                           l2_cache_size=kwargs.get("l2_size", 8192))

        # SPI Flash --------------------------------------------------------------------------------
        if with_spi_flash:
            from litespi.modules import S25FL128S
            from litespi.opcodes import SpiNorFlashOpCodes as Codes
            self.add_spi_flash(mode="4x",
                               module=S25FL128S(Codes.READ_1_1_4),
                               with_master=True)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads=platform.request_all("user_led"),
                sys_clk_freq=sys_clk_freq)
Пример #9
0
    def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_video_terminal=False, **kwargs):
        platform = icebreaker.Platform()
        platform.add_extension(icebreaker.break_off_pmod)

        # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
        kwargs["integrated_sram_size"] = 0
        kwargs["integrated_rom_size"]  = 0

        # Set CPU variant / reset address
        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on iCEBreaker",
            ident_version  = True,
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
        self.submodules.spram = Up5kSPRAM(size=64*kB)
        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))

        # SPI Flash --------------------------------------------------------------------------------
        self.add_spi_flash(mode="1x", dummy_cycles=8)

        # Add ROM linker region --------------------------------------------------------------------
        self.bus.add_region("rom", SoCRegion(
            origin = self.mem_map["spiflash"] + bios_flash_offset,
            size   = 32*kB,
            linker = True)
        )

        # Video ------------------------------------------------------------------------------------
        if with_video_terminal:
            platform.add_extension(icebreaker.dvi_pmod)
            self.submodules.videophy = VideoDVIPHY(platform.request("dvi"), clock_domain="sys")
            self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="sys")

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = platform.request_all("user_led"),
            sys_clk_freq = sys_clk_freq)
Пример #10
0
    def __init__(self,
                 variant="au",
                 sys_clk_freq=int(83333333),
                 with_spi_flash=False,
                 with_led_chaser=True,
                 **kwargs):
        platform = alchitry_au.Platform(variant=variant)

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Alchitry Au(+)",
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
                platform.request("ddram"),
                memtype="DDR3",
                nphases=4,
                sys_clk_freq=sys_clk_freq,
                iodelay_clk_freq=200e6)
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=AS4C128M16(sys_clk_freq, "1:4"),
                           l2_cache_size=kwargs.get("l2_size", 8192))

        # SPI Flash --------------------------------------------------------------------------------
        if with_spi_flash:
            from litespi.modules import SST26VF032B
            from litespi.opcodes import SpiNorFlashOpCodes as Codes
            self.add_spi_flash(mode="4x",
                               module=SST26VF032B(Codes.READ_1_1_1),
                               with_master=True)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads=platform.request_all("user_led"),
                sys_clk_freq=sys_clk_freq)
Пример #11
0
    def __init__(self, variant="a7-35", sys_clk_freq=int(100e6), with_pcie=False,
                 with_ethernet=False, with_led_chaser=True, **kwargs):
        platform = netv2.Platform(variant=variant)

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident = "LiteX SoC on NeTV2",
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
                memtype      = "DDR3",
                nphases      = 4,
                sys_clk_freq = sys_clk_freq)
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = K4B2G1646F(sys_clk_freq, "1:4"),
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

        # Ethernet ---------------------------------------------------------------------------------
        if with_ethernet:
            self.submodules.ethphy = LiteEthPHYRMII(
                clock_pads = self.platform.request("eth_clocks"),
                pads       = self.platform.request("eth"))
            self.add_ethernet(phy=self.ethphy)

        # PCIe -------------------------------------------------------------------------------------
        if with_pcie:
            self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
                data_width = 128,
                bar0_size  = 0x20000)
            self.add_pcie(phy=self.pcie_phy, ndmas=1)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads         = platform.request_all("user_led"),
                sys_clk_freq = sys_clk_freq)
Пример #12
0
    def __init__(self,
                 sys_clk_freq=int(50e6),
                 with_mister_sdram=True,
                 with_mister_video_terminal=False,
                 sdram_rate="1:1",
                 **kwargs):
        platform = de10nano.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on DE10-Nano",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform,
                                   sys_clk_freq,
                                   with_sdram=with_mister_sdram,
                                   sdram_rate=sdram_rate)

        # SDR SDRAM --------------------------------------------------------------------------------
        if with_mister_sdram and not self.integrated_main_ram_size:
            sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
                                                sys_clk_freq)
            self.add_sdram("sdram",
                           phy=self.sdrphy,
                           module=AS4C32M16(sys_clk_freq, sdram_rate),
                           l2_cache_size=kwargs.get("l2_size", 8192))

        # Video Terminal ---------------------------------------------------------------------------
        if with_mister_video_terminal:
            self.submodules.videophy = VideoVGAPHY(platform.request("vga"),
                                                   clock_domain="vga")
            self.add_video_terminal(phy=self.videophy,
                                    timings="800x600@60Hz",
                                    clock_domain="vga")

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
Пример #13
0
    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
        platform = ax7010.Platform()

        #if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB.
        kwargs["uart_name"] = "serial"

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on Alinx AX7010",
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)
        
        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads         = platform.request_all("user_led"),
                sys_clk_freq = sys_clk_freq)
Пример #14
0
    def __init__(self, sys_clk_freq=int(48e6), with_led_chaser=True, **kwargs):
        platform = tang_nano.Platform()

        # SoCMini ----------------------------------------------------------------------------------
        SoCMini.__init__(self, platform, sys_clk_freq,
            ident         = "LiteX SoC on Tang Nano",
            ident_version = True)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # UARTBone ---------------------------------------------------------------------------------
        self.add_uartbone(baudrate=int(1e6)) # CH552 firmware does not support traditional baudrates.

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads         = platform.request_all("user_led"),
                sys_clk_freq = sys_clk_freq)
Пример #15
0
    def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
        platform = mist.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on MIST",
            ident_version  = True,
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # SDR SDRAM --------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
            self.add_sdram("sdram",
                phy                     = self.sdrphy,
                module                  = MT48LC16M16(sys_clk_freq, "1:1"),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x2000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )

        # VGA Terminal -----------------------------------------------------------------------------
        if with_vga:
            self.submodules.terminal = terminal = Terminal()
            self.bus.add_slave("terminal", self.terminal.bus, region=SoCRegion(origin=0x30000000, size=0x10000))
            vga_pads = platform.request("vga")
            self.comb += [
                vga_pads.vsync.eq(terminal.vsync),
                vga_pads.hsync.eq(terminal.hsync),
                vga_pads.r.eq(terminal.red[2:8]),
                vga_pads.g.eq(terminal.green[2:8]),
                vga_pads.b.eq(terminal.blue[2:8])
            ]

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = platform.request_all("user_led"),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")
Пример #16
0
    def __init__(self,
                 revision,
                 sys_clk_freq=int(50e6),
                 with_ethernet=False,
                 with_etherbone=False,
                 eth_ip="192.168.1.50",
                 with_led_chaser=True,
                 **kwargs):
        platform = pano_logic_g2.Platform(revision=revision)
        if with_etherbone:
            sys_clk_freq = int(125e6)

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Pano Logic G2",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform,
                                   sys_clk_freq,
                                   with_ethernet=with_ethernet
                                   or with_etherbone)

        # Ethernet / Etherbone ---------------------------------------------------------------------
        if with_ethernet or with_etherbone:
            self.submodules.ethphy = LiteEthPHY(
                clock_pads=self.platform.request("eth_clocks"),
                pads=self.platform.request("eth"),
                clk_freq=sys_clk_freq,
                with_hw_init_reset=False)
            if with_ethernet:
                self.add_ethernet(phy=self.ethphy)
            if with_etherbone:
                self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads=platform.request_all("user_led"),
                sys_clk_freq=sys_clk_freq)
Пример #17
0
    def __init__(self,
                 sys_clk_freq=int(75e6),
                 hyperram="none",
                 toolchain="radiant",
                 with_led_chaser=True,
                 **kwargs):
        platform = crosslink_nx_vip.Platform(toolchain=toolchain)
        platform.add_platform_command(
            "ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")

        # Disable Integrated SRAM since we want to instantiate LRAM specifically for it
        kwargs["integrated_sram_size"] = 0

        # SoCCore -----------------------------------------_----------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Crosslink-NX VIP Input Board",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        if hyperram == "none":
            # 128KB LRAM (used as SRAM) ------------------------------------------------------------
            size = 128 * kB
            self.submodules.spram = NXLRAM(32, size)
            self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
                              size)
        else:
            # Use HyperRAM generic PHY as SRAM -----------------------------------------------------
            size = 8 * 1024 * kB
            hr_pads = platform.request("hyperram", int(hyperram))
            self.submodules.hyperram = HyperRAM(hr_pads)
            self.register_mem("sram", self.mem_map["sram"], self.hyperram.bus,
                              size)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads=Cat(*[platform.request("user_led", i) for i in range(4)]),
                sys_clk_freq=sys_clk_freq)
Пример #18
0
    def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True,
                 with_video_terminal=False, **kwargs):
        platform = muselab_icesugar.Platform()

        # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
        kwargs["integrated_sram_size"] = 0
        kwargs["integrated_rom_size"]  = 0

        # Set CPU variant / reset address
        kwargs["cpu_variant"]  = "lite"
        kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on Muselab iCESugar",
            ident_version  = True,
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
        self.submodules.spram = Up5kSPRAM(size=64*kB)
        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))

        # SPI Flash --------------------------------------------------------------------------------
        from litespi.modules import W25Q64FV
        from litespi.opcodes import SpiNorFlashOpCodes as Codes
        self.add_spi_flash(mode="1x", module=W25Q64FV(Codes.READ_1_1_1), with_master=False)

        # Add ROM linker region --------------------------------------------------------------------
        self.bus.add_region("rom", SoCRegion(
            origin = self.mem_map["spiflash"] + bios_flash_offset,
            size   = 32*kB,
            linker = True)
        )

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            led_pads = platform.request_all("user_led_n")
            self.submodules.leds = LedChaser(
                pads         = led_pads,
                sys_clk_freq = sys_clk_freq)
Пример #19
0
    def __init__(self,
                 sys_clk_freq=int(50e6),
                 x5_clk_freq=None,
                 toolchain="trellis",
                 **kwargs):
        platform = ecp5_evn.Platform(toolchain=toolchain)

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)

        # CRG --------------------------------------------------------------------------------------
        crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
        self.submodules.crg = crg

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
            sys_clk_freq=sys_clk_freq)
        self.add_csr("leds")
Пример #20
0
    def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False,
                 with_led_chaser=True, with_pmod_gpio=False, **kwargs):
        platform = trellisboard.Platform(toolchain=toolchain)

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident = "LiteX SoC on Trellis Board",
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
        self.submodules.crg = crg_cls(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = ECP5DDRPHY(
                platform.request("ddram"),
                sys_clk_freq=sys_clk_freq)
            self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
            self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
            self.add_sdram("sdram",
                phy           = self.ddrphy,
                module        = MT41J256M16(sys_clk_freq, "1:2"),
                l2_cache_size = kwargs.get("l2_size", 8192),
            )

        # Ethernet ---------------------------------------------------------------------------------
        if with_ethernet:
            self.submodules.ethphy = LiteEthPHYRGMII(
                clock_pads = self.platform.request("eth_clocks"),
                pads       = self.platform.request("eth"))
            self.add_ethernet(phy=self.ethphy)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads         = platform.request_all("user_led"),
                sys_clk_freq = sys_clk_freq)

        # GPIOs ------------------------------------------------------------------------------------
        if with_pmod_gpio:
            platform.add_extension(trellisboard.raw_pmod_io("pmoda"))
            self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
Пример #21
0
    def __init__(self,
                 sys_clk_freq=int(50e6),
                 with_video_terminal=False,
                 **kwargs):
        platform = de10lite.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on DE10-Lite",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # SDR SDRAM --------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
                                               sys_clk_freq)
            self.add_sdram("sdram",
                           phy=self.sdrphy,
                           module=IS42S16320(sys_clk_freq, "1:1"),
                           origin=self.mem_map["main_ram"],
                           size=kwargs.get("max_sdram_size", 0x40000000),
                           l2_cache_size=kwargs.get("l2_size", 8192),
                           l2_cache_min_data_width=kwargs.get(
                               "min_l2_data_width", 128),
                           l2_cache_reverse=True)

        # Video Terminal ---------------------------------------------------------------------------
        if with_video_terminal:
            self.submodules.videophy = VideoVGAPHY(platform.request("vga"),
                                                   clock_domain="vga")
            self.add_video_terminal(phy=self.videophy,
                                    timings="800x600@60Hz",
                                    clock_domain="vga")

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
        self.add_csr("leds")
Пример #22
0
    def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
        sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1",
        with_video_terminal=False, with_video_framebuffer=False, spiflash=False, **kwargs):
        platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
        if spiflash:
            self.mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on ULX3S",
            ident_version  = True,
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        with_usb_pll   = kwargs.get("uart_name", None) == "usb_acm"
        with_video_pll = with_video_terminal or with_video_framebuffer
        self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll, with_video_pll, sdram_rate=sdram_rate)

        # SDR SDRAM --------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
            self.add_sdram("sdram",
                phy              = self.sdrphy,
                module           = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
                size             = 0x40000000,
                l2_cache_size    = kwargs.get("l2_size", 8192),
                l2_cache_reverse = False
            )

        # Video ------------------------------------------------------------------------------------
        if with_video_terminal or with_video_framebuffer:
            self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
            if with_video_terminal:
                self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
            if with_video_framebuffer:
                self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
                self.comb += platform.request("ext0p").eq(self.video_framebuffer.underflow) # FIXME: Remove, used to debug SDRAM underflows.

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = platform.request_all("user_led"),
            sys_clk_freq = sys_clk_freq)
Пример #23
0
    def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs):
        platform = aller.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Aller",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
                platform.request("ddram"),
                memtype="DDR3",
                nphases=4,
                sys_clk_freq=sys_clk_freq,
                iodelay_clk_freq=200e6)
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=MT41J128M16(sys_clk_freq, "1:4"),
                           origin=self.mem_map["main_ram"],
                           size=kwargs.get("max_sdram_size", 0x40000000),
                           l2_cache_size=kwargs.get("l2_size", 8192),
                           l2_cache_min_data_width=kwargs.get(
                               "min_l2_data_width", 128),
                           l2_cache_reverse=True)

        # PCIe -------------------------------------------------------------------------------------
        if with_pcie:
            self.submodules.pcie_phy = S7PCIEPHY(platform,
                                                 platform.request("pcie_x4"),
                                                 data_width=128,
                                                 bar0_size=0x20000)
            self.add_pcie(phy=self.pcie_phy, ndmas=1)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
                                         sys_clk_freq=sys_clk_freq)
Пример #24
0
    def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs):
        platform = lattice_ice40up5k_evn.Platform()

        # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
        kwargs["integrated_sram_size"] = 0
        kwargs["integrated_rom_size"]  = 0

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident = "LiteX SoC on Lattice iCE40UP5k EVN breakout board",
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
        self.submodules.spram = Up5kSPRAM(size=128*kB)
        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))

        # SPI Flash --------------------------------------------------------------------------------
        # 4x mode is not possible on this board since WP and HOLD pins are not connected to the FPGA
        from litespi.modules import N25Q032A
        from litespi.opcodes import SpiNorFlashOpCodes as Codes
        self.add_spi_flash(mode="1x", module=N25Q032A(Codes.READ_1_1_1))

        # Add ROM linker region --------------------------------------------------------------------
        self.bus.add_region("rom", SoCRegion(
            origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
            size   = 32*kB,
            linker = True)
        )
        self.cpu.set_reset_address(self.bus.regions["rom"].origin)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads         = platform.request_all("user_led_n"),
                sys_clk_freq = sys_clk_freq)

        # Add a UARTBone bridge --------------------------------------------------------------------
        debug_uart = False
        if debug_uart:
            self.add_uartbone(name="serial")
Пример #25
0
    def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, toolchain="trellis", **kwargs):
        platform = versa_ecp5.Platform(toolchain=toolchain, device=device)

        # FIXME: adapt integrated rom size for Microwatt
        if kwargs.get("cpu_type", None) == "microwatt":
            kwargs["integrated_rom_size"] = 0xb000 if with_ethernet else 0x9000

        # SoCCore -----------------------------------------_----------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = ECP5DDRPHY(
                platform.request("ddram"),
                sys_clk_freq=sys_clk_freq)
            self.add_csr("ddrphy")
            self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
            self.add_sdram("sdram",
                phy                     = self.ddrphy,
                module                  = MT41K64M16(sys_clk_freq, "1:2"),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )

        # Ethernet ---------------------------------------------------------------------------------
        if with_ethernet:
            self.submodules.ethphy = LiteEthPHYRGMII(
                clock_pads = self.platform.request("eth_clocks"),
                pads       = self.platform.request("eth"))
            self.add_csr("ethphy")
            self.add_ethernet(phy=self.ethphy)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")
Пример #26
0
    def __init__(self,
                 sys_clk_freq=int(100e6),
                 with_led_chaser=True,
                 **kwargs):
        platform = zybo_z7.Platform()

        if kwargs["uart_name"] == "serial":
            kwargs["uart_name"] = "usb_uart"  # Use USB-UART Pmod on JB.

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Zybo Z7",
                         ident_version=True,
                         **kwargs)

        # Zynq7000 Integration ---------------------------------------------------------------------
        if kwargs.get("cpu_type", None) == "zynq7000":
            # Get and set the pre-generated .xci FIXME: change location? add it to the repository?
            os.system(
                "wget https://github.com/litex-hub/litex-boards/files/4967144/zybo_z7_ps7.txt"
            )
            os.makedirs("xci", exist_ok=True)
            os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
            self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")

            # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
            wb_gp0 = wishbone.Interface()
            self.submodules += axi.AXI2Wishbone(
                axi=self.cpu.add_axi_gp_master(),
                wishbone=wb_gp0,
                base_address=0x43c00000)
            self.add_wb_master(wb_gp0)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads=platform.request_all("user_led"),
                sys_clk_freq=sys_clk_freq)
Пример #27
0
    def __init__(self, platform, with_ethernet=False, with_led_chaser=True, **kwargs):
        sys_clk_freq = int(1e9/platform.default_clk_period)

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident = "LiteX Simple SoC",
            **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        # Leds -------------------------------------------------------------------------------------
        try:
            if with_led_chaser:
                self.submodules.leds = LedChaser(
                    pads         = platform.request_all("user_led"),
                    sys_clk_freq = sys_clk_freq)
        except:
            pass
Пример #28
0
    def __init__(self, variant="z7-20", sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
        platform = digilent_arty_z7.Platform(variant)

        if kwargs.get("cpu_type", None) == "zynq7000":
            kwargs['integrated_sram_size'] = 0
            kwargs['with_uart'] = False
            self.mem_map = {
                'csr': 0x4000_0000,  # Zynq GP0 default
            }

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident = "LiteX SoC on Arty Z7",
            **kwargs)

        # Zynq7000 Integration ---------------------------------------------------------------------
        if kwargs.get("cpu_type", None) == "zynq7000":
            preset_name = "arty_z7_20.tcl" if variant == "z7-20" else "arty_z7_10.tcl"

            os.system("wget http://kmf2.trabucayre.com/" + preset_name)
            self.cpu.set_ps7(preset=preset_name)

            # Connect AXI GP0 to the SoC
            wb_gp0 = wishbone.Interface()
            self.submodules += axi.AXI2Wishbone(
                axi          = self.cpu.add_axi_gp_master(),
                wishbone     = wb_gp0,
                base_address = self.mem_map['csr'])
            self.add_wb_master(wb_gp0)

            use_ps7_clk = True
        else:
            use_ps7_clk = False

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.submodules.leds = LedChaser(
                pads         = platform.request_all("user_led"),
                sys_clk_freq = sys_clk_freq)
Пример #29
0
    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
        platform = alveo_u250.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self,
                         platform,
                         sys_clk_freq,
                         ident="LiteX SoC on Alveo U250",
                         ident_version=True,
                         **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR4 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = usddrphy.USPDDRPHY(
                platform.request("ddram"),
                memtype="DDR4",
                sys_clk_freq=sys_clk_freq,
                iodelay_clk_freq=500e6,
                cmd_latency=1,
                is_rdimm=True)
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                           phy=self.ddrphy,
                           module=MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
                           origin=self.mem_map["main_ram"],
                           size=kwargs.get("max_sdram_size", 0x40000000),
                           l2_cache_size=kwargs.get("l2_size", 8192),
                           l2_cache_min_data_width=kwargs.get(
                               "min_l2_data_width", 128),
                           l2_cache_reverse=True)

        # Firmware RAM (To ease initial LiteDRAM calibration support) ------------------------------
        self.add_ram("firmware_ram", 0x20000000, 0x8000)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads=Cat(*[platform.request("user_led", i) for i in range(3)]),
            sys_clk_freq=sys_clk_freq)
        self.add_csr("leds")
Пример #30
0
    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
        platform = kcu105.Platform()

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)

        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR4 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
                memtype          = "DDR4",
                sys_clk_freq     = sys_clk_freq,
                iodelay_clk_freq = 200e6,
                cmd_latency      = 1)
            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                phy                     = self.ddrphy,
                module                  = EDY4016A(sys_clk_freq, "1:4"),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )

        # Ethernet ---------------------------------------------------------------------------------
        if with_ethernet:
            self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
                data_pads    = self.platform.request("sfp", 0),
                sys_clk_freq = self.clk_freq)
            self.add_csr("ethphy")
            self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
            self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
            self.add_ethernet(phy=self.ethphy)

        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
            pads         = Cat(*[platform.request("user_led", i) for i in range(8)]),
            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")