def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_led_chaser=True,
with_pcie=False, **kwargs):
platform = adi_adrv2crr_fmc.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ADI ADRV2CRR-FMC",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq, ddram_channel)
# DDR4 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USPDDRPHY(
pads = platform.request("ddram", ddram_channel),
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 400e6)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT40A512M16(sys_clk_freq, "1:4"),
size = 0x40000000,
l2_cache_size = kwargs.get("l2_size", 8192)
)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
assert self.csr_data_width == 32
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
speed = "gen3",
data_width = 128,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Fan --------------------------------------------------------------------------------------
# Full speed is _really_ loud and with this demo bitstream which is almost
# empty, we can slow it way down and still keep the FPGA < 10C above ambient
self.submodules.fan = PWM(
default_enable = 1,
default_period = 2500,
default_width = 500
)
self.comb += platform.request("fan").pwm_n.eq(~self.fan.pwm)
# SYSMON -----------------------------------------------------------------------------------
self.submodules.sysmon = ZynqUSPSystemMonitor()
# JTAG -------------------------------------------------------------------------------------
self.add_jtagbone()
def add_pwm(self, default_width=512, default_period=1024, with_csr=True):
from litex.soc.cores.pwm import PWM
self.submodules.pwm = PWM(with_csr=with_csr,
default_enable=1,
default_width=default_width,
default_period=default_period)
# Use PWM as Output Enable for pads.
self.comb += If(~self.pwm.pwm, self.pads.eq(0))
def __init__(self,
sys_clk_freq=int(100e6),
with_pwm=False,
with_gpio=False,
gpio_width=32,
with_spi_master=False,
spi_master_data_width=8,
spi_master_clk_freq=8e6,
**kwargs):
platform = Platform(_io)
# UART
if kwargs["with_uart"]:
platform.add_extension([(
"serial",
0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
)])
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"),
rst=platform.request("sys_rst"))
# SoCMini ----------------------------------------------------------------------------------
print(kwargs)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SPI Master
if with_spi_master:
platform.add_extension([(
"spi_master",
0,
Subsignal("clk", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("mosi", Pins(1)),
Subsignal("miso", Pins(1)),
)])
self.submodules.spi_master = SPIMaster(
pads=platform.request("spi_master"),
data_width=spi_master_data_width,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=spi_master_clk_freq,
)
self.add_csr("spi_master")
# PWM
if with_pwm:
platform.add_extension([("pwm", 0, Pins(1))])
self.submodules.pwm = PWM(platform.request("pwm"))
self.add_csr("pwm")
# GPIO
if with_gpio:
platform.add_extension([("gpio", 0, Pins(gpio_width))])
self.submodules.gpio = GPIOTristate(platform.request("gpio"))
self.add_csr("gpio")
# Wishbone Master
if kwargs["bus"] == "wishbone":
wb_bus = wishbone.Interface()
self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb"))
wb_pads = platform.request("wb")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# AXI-Lite Master
if kwargs["bus"] == "axi":
axi_bus = axi.AXILiteInterface(data_width=32, address_width=32)
wb_bus = wishbone.Interface()
axi2wb = axi.AXILite2Wishbone(axi_bus, wb_bus)
self.submodules += axi2wb
self.bus.add_master(master=wb_bus)
platform.add_extension(axi_bus.get_ios("axi"))
axi_pads = platform.request("axi")
self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave")
# IRQs
for name, loc in sorted(self.irq.locs.items()):
module = getattr(self, name)
platform.add_extension([("irq_" + name, 0, Pins(1))])
irq_pin = platform.request("irq_" + name)
self.comb += irq_pin.eq(module.ev.irq)
def add_rgb_led(self):
rgb_led_pads = self.platform.request("rgb_led", 0)
for n in "rgb":
setattr(self.submodules, "rgb_led_{}0".format(n), PWM(getattr(rgb_led_pads, n)))
self.add_csr("rgb_led_{}0".format(n))
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
# Timer ---------------------------------------------------------------
# If timer0 is enabled ensure that update timer is available also
if "with_timer" in kwargs:
with_timer = kwargs.get("with_timer")
if with_timer:
kwargs["timer_uptime"] = True
self.platform = Platform
# SoCCore -------------------------------------------------------------
SoCCore.__init__(self, self.platform, clk_freq=sys_clk_freq, **kwargs)
#self.mem_map = {**self.mem_map, **{
# "spiflash": 0xd0_000_000
#}}
# CRG -----------------------------------------------------------------
eth0_clock = self.platform.request("eth_clocks_ext", 0)
eth1_clock = self.platform.request("eth_clocks_ext", 1)
eth2_clock = self.platform.request("eth_clocks_ext", 2)
eth3_clock = self.platform.request("eth_clocks_ext", 3)
self.submodules.crg = _CRG(self.platform, sys_clk_freq, eth0_clock,
eth1_clock, eth2_clock, eth3_clock)
# DDR3 SDRAM ----------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
self.platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# SPI Flash -----------------------------------------------------------
# Disabled due to rom size limitations
#SPIFLASH_PAGE_SIZE = 256
#SPIFLASH_SECTOR_SIZE = 64 * 1024
#SPIFLASH_DUMMY_CYCLES = 11
#self.add_spi_flash(dummy_cycles=SPIFLASH_DUMMY_CYCLES)
#self.add_constant("SPIFLASH_PAGE_SIZE", SPIFLASH_PAGE_SIZE)
#self.add_constant("SPIFLASH_SECTOR_SIZE", SPIFLASH_SECTOR_SIZE)
## Place firmware in second half of 16MB SPI flash. First half is
## used for FPGA bitstream
#self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map["spiflash"] + 0x800000)
# SPI SD-Card ---------------------------------------------------------
self.add_spi_sdcard(name="spisdcard", spi_clk_freq=400e3)
# Hello World ---------------------------------------------------------
self.submodules.hello = Hello()
self.csr.add("hello")
# GPIO ----------------------------------------------------------------
#pd = self.platform.request("pmodd")
#self.submodules.pmodd = GPIOInOut(in_signal=pd, out_signal=pd)
#self.csr.add("pmodd")
# Misc GPIO -----------------------------------------------------------
self.submodules.leds = GPIOOut(
Cat(platform_request_all(self.platform, "user_led")))
self.add_csr("leds")
rgb_led_pads = self.platform.request("rgb_led", 0)
for n in "rgb":
setattr(self.submodules, "rgb_led_{}0".format(n),
PWM(getattr(rgb_led_pads, n)))
self.add_csr("rgb_led_{}0".format(n))
self.submodules.switches = GPIOIn(
Cat(platform_request_all(self.platform, "user_sw")))
self.add_csr("switches")
# Ethernet ------------------------------------------------------------
# Loval IP4 address of Ethernet interface 1 (10.0.0.50)
self.add_constant("LOCALIP1", 10)
self.add_constant("LOCALIP2", 0)
self.add_constant("LOCALIP3", 0)
self.add_constant("LOCALIP4", 50)
# IP4 Address of TFTP boot server (10.0.0.100)
self.add_constant("REMOTEIP1", 10)
self.add_constant("REMOTEIP2", 0)
self.add_constant("REMOTEIP3", 0)
self.add_constant("REMOTEIP4", 100)
# Ethernet interface 0 (used for TFTP boot).
# Name it "ethphy" and "ethmac" to be recognized by
# BIOS for tftp boot option. Also if it is the only
# interface in the system you MUST remove the 'phy_cd'
# attribute from add_ethernet (or set it to "eth") otherwise
# build fails. When using external ref_clock set clock_pads
# to None and provide a clock domain name for the external
# clock via refclk_cd.
self.submodules.ethphy = LiteEthPHYRMII(clock_pads=None,
pads=self.platform.request(
"eth", 0),
with_hw_init_reset=True,
refclk_cd="eth0")
self.add_csr("ethphy")
self.add_ethernet(name="ethmac", phy=self.ethphy, phy_cd="ethphy_eth")
# Ethernet interface 1
self.submodules.ethphy1 = LiteEthPHYRMII(clock_pads=None,
pads=self.platform.request(
"eth", 1),
with_hw_init_reset=True,
refclk_cd="eth1")
self.add_csr("ethphy1")
self.add_ethernet(name="ethmac1",
phy=self.ethphy1,
phy_cd="ethphy1_eth")
# Ethernet interface 2
self.submodules.ethphy2 = LiteEthPHYRMII(clock_pads=None,
pads=self.platform.request(
"eth", 2),
with_hw_init_reset=True,
refclk_cd="eth2")
self.add_csr("ethphy2")
self.add_ethernet(name="ethmac2",
phy=self.ethphy2,
phy_cd="ethphy2_eth")
# Ethernet interface 3
self.submodules.ethphy3 = LiteEthPHYRMII(clock_pads=None,
pads=self.platform.request(
"eth", 3),
with_hw_init_reset=True,
refclk_cd="eth3")
self.add_csr("ethphy3")
# Disabled becaused used for etherbone down below
#self.add_ethernet(name="ethmac3", phy=self.ethphy3, phy_cd="ethphy3_eth")
# ticker --------------------------------------------------------------
self.submodules.ticker = Ticker(CLK_FRQ_HZ=sys_clk_freq)
self.csr.add("ticker")
# random --------------------------------------------------------------
self.submodules.random = Random()
self.csr.add("random")
# lite-scope debugger -------------------------------------------------
self.add_etherbone(phy=self.ethphy3,
phy_cd="ethphy3_eth",
ip_address="10.0.0.42",
mac_address=0x10e2d5000001,
udp_port=4711)
# CPU signals
analyzer_signals = [
self.cpu.ibus.stb, self.cpu.ibus.cyc, self.cpu.ibus.adr,
self.cpu.ibus.we, self.cpu.ibus.ack, self.cpu.ibus.sel,
self.cpu.ibus.dat_w, self.cpu.ibus.dat_r
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
sys_clk_freq=int(100e6),
with_pwm=False,
with_mmcm=False,
with_gpio=False,
gpio_width=32,
with_spi_master=False,
spi_master_data_width=8,
spi_master_clk_freq=8e6,
**kwargs):
platform = Platform(_io)
# UART
if kwargs["with_uart"]:
platform.add_extension([(
"serial",
0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
)])
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"),
rst=platform.request("sys_rst"))
# SoCMini ----------------------------------------------------------------------------------
print(kwargs)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# MMCM
if with_mmcm:
platform.add_extension([(
"clkgen",
0,
Subsignal("ref", Pins(1)),
Subsignal("out0", Pins(1)),
Subsignal("out1", Pins(1)),
Subsignal("locked", Pins(1)),
)])
self.clock_domains.cd_out0 = ClockDomain(reset_less=True)
self.clock_domains.cd_out1 = ClockDomain(reset_less=True)
self.submodules.mmcm = mmcm = S7MMCM()
mmcm.expose_drp()
self.add_csr("mmcm")
clkgen = platform.request("clkgen")
mmcm.register_clkin(clkgen.ref, 100e6)
mmcm.create_clkout(self.cd_out0, 148.5e6, with_reset=False)
mmcm.create_clkout(self.cd_out1, 742.5e6, with_reset=False)
self.comb += [
clkgen.out0.eq(self.cd_out0.clk),
clkgen.out1.eq(self.cd_out1.clk),
clkgen.locked.eq(mmcm.locked),
]
# SPI Master
if with_spi_master:
platform.add_extension([(
"spi_master",
0,
Subsignal("clk", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("mosi", Pins(1)),
Subsignal("miso", Pins(1)),
)])
self.submodules.spi_master = SPIMaster(
pads=platform.request("spi_master"),
data_width=spi_master_data_width,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=spi_master_clk_freq,
)
self.add_csr("spi_master")
# PWM
if with_pwm:
platform.add_extension([("pwm", 0, Pins(1))])
self.submodules.pwm = PWM(platform.request("pwm"))
self.add_csr("pwm")
# GPIO
if with_gpio:
platform.add_extension([("gpio", 0, Pins(gpio_width))])
self.submodules.gpio = GPIOTristate(platform.request("gpio"))
self.add_csr("gpio")
# Wishbone Master
if kwargs["bus"] in ["wishbone"]:
wb_bus = wishbone.Interface()
self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb"))
wb_pads = platform.request("wb")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# AXI-Lite Master
if kwargs["bus"] in ["axi", "axi_lite"]:
axi_bus = axi.AXILiteInterface(data_width=32, address_width=32)
wb_bus = wishbone.Interface()
axi2wb = axi.AXILite2Wishbone(axi_bus, wb_bus)
self.submodules += axi2wb
self.bus.add_master(master=wb_bus)
platform.add_extension(axi_bus.get_ios("axi"))
axi_pads = platform.request("axi")
self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave")
# IRQs
for name, loc in sorted(self.irq.locs.items()):
module = getattr(self, name)
platform.add_extension([("irq_" + name, 0, Pins(1))])
irq_pin = platform.request("irq_" + name)
self.comb += irq_pin.eq(module.ev.irq)
def add_rgb_led(self):
rgb_led_pads = self.platform.request("rgb_led", 0)
setattr(self.submodules, "rgb_led_r0",
PWM(getattr(rgb_led_pads, 'r')))