def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, with_video_framebuffer=False, **kwargs): platform = basys3.Platform() # SoCCore ----------------------------------_----------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Basys3", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_video_terminal=False, **kwargs): platform = ego1.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on EGO1 Board", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # VGA terminal ----------------------------------------------------------------------------- if with_video_terminal: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_mister_sdram=True, with_mister_video_terminal=False, sdram_rate="1:1", **kwargs): platform = de10nano.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on DE10-Nano", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=with_mister_sdram, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if with_mister_sdram and not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = AS4C32M16(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) ) # Video Terminal --------------------------------------------------------------------------- if with_mister_video_terminal: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False, **kwargs): platform = mist.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on MIST", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = MT48LC16M16(sys_clk_freq, "1:1"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, **kwargs): platform = nexys4ddr.Platform() # SoCCore ----------------------------------_----------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Nexys4DDR", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR2 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT47H64M16(sys_clk_freq, "1:2"), l2_cache_size=kwargs.get("l2_size", 8192)) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), revision="revd", sdram_rate="1:2", mister_sdram=None, with_led_chaser=True, with_video_terminal=False, **kwargs): platform = terasic_sockit.Platform(revision) # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "jtag_uart" # Defaults to JTAG-UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on the Terasic SoCKit", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate, with_video_terminal=with_video_terminal) # SDR SDRAM -------------------------------------------------------------------------------- if mister_sdram is not None: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY sdrphy_mod = { "xs_v22": W9825G6KH6, "xs_v24": AS4C32M16 }[mister_sdram] self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy=self.sdrphy, module=sdrphy_mod(sys_clk_freq, sdram_rate), l2_cache_size=kwargs.get("l2_size", 8192)) # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: vga_pads = platform.request("vga") self.comb += [vga_pads.sync_n.eq(0), vga_pads.blank_n.eq(1)] self.specials += DDROutput(i1=1, i2=0, o=vga_pads.clk, clk=ClockSignal("vga")) self.submodules.videophy = VideoVGAPHY(vga_pads, clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(75e6), with_led_chaser=True, with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs): platform = digilent_nexys4.Platform() # SoCCore ----------------------------------_----------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Nexys4", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Cellular RAM ------------------------------------------------------------------------------- addCellularRAM(self, platform, "main_ram", 0x40000000) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYRMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(105e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, sdram_rate="1:1", **kwargs): platform = qmtech_5cefa2.Platform(with_daughterboard=with_daughterboard) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTECH 5CEFA2" + (" + Daughterboard" if with_daughterboard else ""), **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet = with_ethernet or with_etherbone, with_vga = with_video_terminal or with_video_framebuffer, sdram_rate = sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs): platform = de10lite.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE10-Lite", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy=self.sdrphy, module=IS42S16320(sys_clk_freq, "1:1"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq) self.add_csr("leds")
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, ident_version=True, with_jtagbone=True, with_mapped_flash=False, **kwargs): platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTech XC7A35T" + (" + Daughterboard" if with_daughterboard else ""), ident_version = ident_version, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # The daughterboard has the tx clock wired to a non-clock pin, so we can't help it self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]") # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # Flash (through LiteSPI, experimental). if with_mapped_flash: self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), MT25QL128(Codes.READ_1_1_1)) self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.cpu.endianness) spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=MT25QL128.total_size, cached=False) self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) if not with_daughterboard and kwargs["uart_name"] == "serial": kwargs["uart_name"] = "jtag_serial"
def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis", with_led_chaser = True, with_video_terminal = True, with_video_framebuffer = False, **kwargs): platform = ecp5_vip.Platform(toolchain=toolchain) #bios_flash_offset = 0x400000 # Set CPU variant / reset address #kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset kwargs["integrated_rom_size"] = 0x10000 # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on ECP5 Evaluation Board", #integrated_main_ram_size = 0x4000, #integrated_main_ram_size = 0, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K64M16(sys_clk_freq, "1:2"), # Not entirely MT41J64M16 but similar and works(c) l2_cache_size = kwargs.get("l2_size", 8192), ) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: pads = platform.request("hdmi") self.submodules.videophy = VideoVGAPHY(pads, clock_domain="hdmi") self.submodules.videoi2c = I2CMaster(pads) # # 1920x1080@60Hz # pixel_clock_hz = 160e6 # framerate_hz = 60 # pixels_horizontal = 2200 # pixels_vertical = 1125 # 800x600@60Hz pixel_clock_hz = 40e6 framerate_hz = 60 pixels_horizontal = 1056 pixels_vertical = 628 # # 1920x1080@30Hz # pixel_clock_hz = 80e6 # framerate_hz = 30 # pixels_horizontal = 2640 # pixels_vertical = 1125 self.videoi2c.add_init(addr=0x3B, init=[ (0xc7, 0x00), # HDMI configuration (0xc7, 0x00), # Write twice, the first transfer fails for some reason (0x1e, 0x00), # Power up transmitter (0x08, 0x60), # Input Bus/Pixel Repetition (default) (0x00, int((pixel_clock_hz/1e4) %256)), # Pixel clock in MHz * 100 (0x01, int((pixel_clock_hz/1e4)//256)), # (0x02, int((framerate_hz*100) %256)), # Framerate * 100 (0x03, int((framerate_hz*100)//256)), # (0x04, int((pixels_horizontal) %256)), # Pixels horizontal (0x05, int((pixels_horizontal)//256)), # (0x06, int((pixels_vertical) %256)), # Pixels vertical (0x07, int((pixels_vertical)//256)), # (0x1a, 0x00) # end ]) if with_video_terminal: #self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi") #self.add_video_terminal(phy=self.videophy, timings="1920x1080@30Hz", clock_domain="hdmi") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") if with_video_framebuffer: #self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, variant, version, sys_clk_freq, trng, usb, sdram, engine, i2c, bw2, cg3, cg6, cg3_res, sdcard, **kwargs): framebuffer = (bw2 or cg3 or cg6) print(f"Building SBusFPGA for board version {version}") kwargs["cpu_type"] = "None" kwargs["integrated_sram_size"] = 0 kwargs["with_uart"] = False kwargs["with_timer"] = False self.sys_clk_freq = sys_clk_freq self.platform = platform = ztex213_sbus.Platform(variant=variant, version=version) if (framebuffer and (version == "V1.2")): platform.add_extension(ztex213_sbus._vga_pmod_io_v1_2) if (framebuffer): hres = int(cg3_res.split("@")[0].split("x")[0]) vres = int(cg3_res.split("@")[0].split("x")[1]) if (bw2): cg3_fb_size = bw2_fb.bw2_rounded_size(hres, vres) else: cg3_fb_size = cg3_fb.cg3_rounded_size(hres, vres) print( f"Reserving {cg3_fb_size} bytes ({cg3_fb_size//1048576} MiB) for the CG3/CG6" ) else: hres = 0 vres = 0 cg3_fb_size = 0 litex.soc.cores.video.video_timings.update(cg3_fb.cg3_timings) # if there's just one DVMA bus master in the design, # then we'll connect it directly to the wishbone interface # in the FSM rather than to the system Wishbone bus # sdcard has two by itself, so never a single_dvma_master single_dvma_master = False if (usb and not engine and not sdcard): # fixme: others? single_dvma_master = True if (engine and not usb and not sdcard): # fixme: others? single_dvma_master = True SoCCore.__init__( self, platform=platform, sys_clk_freq=sys_clk_freq, clk_freq=sys_clk_freq, csr_paging=0x1000, # default is 0x800 **kwargs) # *** This mem-map is also exposed in the FSM (matched prefixes) *** # and in the PROM (to tell NetBSD where everything is) # Currently it is a straight mapping between the two: # the physical address here are used as offset in the SBus # reserved area of 256 MiB # Anything at 0x10000000 is therefore unreachable directly # The position of the 'dvma_bridge' is so it overlaps # the virtual address space used by NetBSD DMA allocators # (themselves constrained by the SBus MMU capabilities) self.wb_mem_map = wb_mem_map = { "prom": 0x00000000, # 256 Kib ought to be enough for anybody (we're using < 8 Kib now...) "csr": 0x00040000, "usb_host": 0x00080000, # OHCI registers are here, not in CSR #"usb_shared_mem": 0x00090000, # unused ATM "curve25519engine": 0x000a0000, # includes microcode (4 KiB@0) and registers (16 KiB @ 64 KiB) "cg6_bt": 0x00200000, # required for compatibility, bt_regs for cg6 #"cg6_dhc": 0x00240000, # required for compatibility, unused "cg6_alt": 0x00280000, # required for compatibility "cg6_fhc": 0x00300000, # required for compatibility #"cg6_thc": 0x00301000, # required for compatibility "cg3_bt": 0x00400000, # required for compatibility, bt_regs for cg3 & bw2 "cg6_accel_rom": 0x00410000, # R5 microcode "cg6_accel_ram": 0x00420000, # R5 microcode working space (stack) "cg6_fbc": 0x00700000, # required for compatibility #"cg6_tec": 0x00701000, # required for compatibility "cg3_pixels": 0x00800000, # required for compatibility, 1/2/4/8 MiB for now (up to 0x00FFFFFF inclusive) (bw2, cg3 and cg6 idem) "main_ram": 0x80000000, # not directly reachable from SBus mapping (only 0x0 - 0x10000000 is accessible), "video_framebuffer": 0x80000000 + 0x10000000 - cg3_fb_size, # Updated later "dvma_bridge": 0xfc000000, # required to match DVMA virtual addresses } self.mem_map.update(wb_mem_map) self.submodules.crg = _CRG( platform=platform, sys_clk_freq=sys_clk_freq, usb=usb, usb_clk_freq=48e6, engine=engine, framebuffer=framebuffer, pix_clk=litex.soc.cores.video.video_timings[cg3_res]["pix_clk"]) #self.platform.add_period_constraint(self.platform.lookup_request("SBUS_3V3_CLK", loose=True), 1e9/25e6) # SBus max ## add our custom timings after the clocks have been defined xdc_timings_filename = None if (version == "V1.0"): xdc_timings_filename = "/home/dolbeau/SBusFPGA/sbus-to-ztex-gateware/sbus-to-ztex-timings.xdc" self.platform.add_extension(ztex213_sbus._usb_io_v1_0) elif (version == "V1.2"): xdc_timings_filename = "/home/dolbeau/SBusFPGA/sbus-to-ztex-gateware/sbus-to-ztex-timings-V1_2.xdc" if (xdc_timings_filename != None): xdc_timings_file = open(xdc_timings_filename) xdc_timings_lines = xdc_timings_file.readlines() for line in xdc_timings_lines: if (line[0:3] == "set"): fix_line = line.strip().replace("{", "{{").replace("}", "}}") #print(fix_line) platform.add_platform_command(fix_line) if (version == "V1.0"): self.submodules.leds = LedChaser( pads=platform.request("SBUS_DATA_OE_LED_2"), sys_clk_freq=sys_clk_freq) self.add_csr("leds") if (usb): self.add_usb_host_custom(pads=platform.request("usb"), usb_clk_freq=48e6, single_dvma_master=single_dvma_master) pad_usb_interrupt = platform.get_irq(irq_req=3, device="usb_host", next_down=True, next_up=False) if (pad_usb_interrupt is None): print(" ***** ERROR ***** USB requires an interrupt") assert (False) sig_usb_interrupt = Signal(reset=1) # the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt) self.comb += pad_usb_interrupt.eq(sig_usb_interrupt) self.comb += sig_usb_interrupt.eq(~self.usb_host.interrupt) ## #pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED") #SBUS_DATA_OE_LED_o = Signal() #self.comb += pad_SBUS_DATA_OE_LED.eq(SBUS_DATA_OE_LED_o) #pad_SBUS_DATA_OE_LED_2 = platform.request("SBUS_DATA_OE_LED_2") #SBUS_DATA_OE_LED_2_o = Signal() #self.comb += pad_SBUS_DATA_OE_LED_2.eq(SBUS_DATA_OE_LED_2_o) #self.comb += SBUS_DATA_OE_LED_o.eq(~SBUS_3V3_INT1s_o) prom_file = "prom_{}.fc".format(version.replace(".", "_")) #prom_file = "SUNW,501-2325.bin" # real TGX #prom_file = "SUNW,501-1415.bin" # real cg3 #prom_file = "SUNW,501-2253.bin" # real TGX+ prom_data = soc_core.get_mem_data(prom_file, "big") # prom = Array(prom_data) #print("\n****************************************\n") #for i in range(len(prom)): # print(hex(prom[i])) #print("\n****************************************\n") self.add_ram( "prom", origin=self.mem_map["prom"], size=2**15, contents=prom_data, mode="r" ) ### FIXME: round up the prom_data size & check for <= 2**16! #getattr(self,"prom").mem.init = prom_data #getattr(self,"prom").mem.depth = 2**15 self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram( "sdram", phy=self.ddrphy, module=MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size=0, ) avail_sdram = self.bus.regions["main_ram"].size ###from sdram_init import DDR3FBInit ###self.submodules.sdram_init = DDR3FBInit(sys_clk_freq=sys_clk_freq, bitslip=1, delay=25) ###self.bus.add_master(name="DDR3Init", master=self.sdram_init.bus) base_fb = self.wb_mem_map[ "main_ram"] + avail_sdram - 1048576 # placeholder if (framebuffer): if (avail_sdram >= cg3_fb_size): avail_sdram = avail_sdram - cg3_fb_size base_fb = self.wb_mem_map["main_ram"] + avail_sdram self.wb_mem_map["video_framebuffer"] = base_fb else: print( "***** ERROR ***** Can't have a FrameBuffer without main ram\n" ) assert (False) # don't enable anything on the SBus side for 20 seconds after power up # this avoids FPGA initialization messing with the cold boot process # requires us to reset the SPARCstation afterward so the FPGA board # is properly identified - or to 'probe-slot' # This is in the 'native' ClockDomain that is never reset hold_reset_ctr = Signal(30, reset=960000000) self.sync.native += If(hold_reset_ctr > 0, hold_reset_ctr.eq(hold_reset_ctr - 1)) hold_reset = Signal(reset=1) self.comb += hold_reset.eq(~(hold_reset_ctr == 0)) # Interface SBus to wishbone # we need to cross clock domains wishbone_slave_sbus = wishbone.Interface( data_width=self.bus.data_width) wishbone_master_sys = wishbone.Interface( data_width=self.bus.data_width) self.submodules.wishbone_master_sbus = WishboneDomainCrossingMaster( platform=self.platform, slave=wishbone_master_sys, cd_master="sbus", cd_slave="sys") self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster( platform=self.platform, slave=wishbone_slave_sbus, cd_master="sys", cd_slave="sbus") # SPARCstation 20 slave interface to the main memory are limited to 32-bytes burst (32-bits wide, 8 word long) # burst_size=16 should work on Ultra systems, but then they probably should go for 64-bits ET as well... # Older systems are probably limited to burst_size=4, (it should always be available) burst_size = 8 data_width = burst_size * 4 data_width_bits = burst_size * 32 blk_addr_width = 32 - log2_int(data_width) self.tosbus_layout = [ ("address", 32), ("data", data_width_bits), ] self.fromsbus_layout = [ ("blkaddress", blk_addr_width), ("data", data_width_bits), ] self.fromsbus_req_layout = [ ("blkaddress", blk_addr_width), ("dmaaddress", 32), ] self.submodules.tosbus_fifo = ClockDomainsRenamer({ "read": "sbus", "write": "sys" })(AsyncFIFOBuffered(width=layout_len(self.tosbus_layout), depth=burst_size)) self.submodules.fromsbus_fifo = ClockDomainsRenamer({ "write": "sbus", "read": "sys" })(AsyncFIFOBuffered(width=layout_len(self.fromsbus_layout), depth=burst_size)) self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({ "read": "sbus", "write": "sys" })(AsyncFIFOBuffered(width=layout_len(self.fromsbus_req_layout), depth=burst_size)) if (sdram): self.submodules.dram_dma_writer = LiteDRAMDMAWriter( port=self.sdram.crossbar.get_port(mode="write", data_width=data_width_bits), fifo_depth=4, fifo_buffered=True) self.submodules.dram_dma_reader = LiteDRAMDMAReader( port=self.sdram.crossbar.get_port(mode="read", data_width=data_width_bits), fifo_depth=4, fifo_buffered=True) self.submodules.exchange_with_mem = ExchangeWithMem( soc=self, platform=platform, tosbus_fifo=self.tosbus_fifo, fromsbus_fifo=self.fromsbus_fifo, fromsbus_req_fifo=self.fromsbus_req_fifo, dram_dma_writer=self.dram_dma_writer, dram_dma_reader=self.dram_dma_reader, mem_size=avail_sdram // 1048576, burst_size=burst_size, do_checksum=False) pad_sdram_interrupt = platform.get_irq(irq_req=4, device="sdram", next_down=True, next_up=False) if (pad_sdram_interrupt is None): print(" ***** ERROR ***** sdram requires an interrupt") assert (False) sig_sdram_interrupt = Signal(reset=1) # the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt) self.comb += pad_sdram_interrupt.eq(sig_sdram_interrupt) self.comb += sig_sdram_interrupt.eq( ~self.exchange_with_mem.irq) ## _sbus_bus = SBusFPGABus(soc=self, platform=self.platform, hold_reset=hold_reset, wishbone_slave=wishbone_slave_sbus, wishbone_master=self.wishbone_master_sbus, tosbus_fifo=self.tosbus_fifo, fromsbus_fifo=self.fromsbus_fifo, fromsbus_req_fifo=self.fromsbus_req_fifo, version=version, burst_size=burst_size, cg3_fb_size=cg3_fb_size, cg3_base=base_fb) #self.submodules.sbus_bus = _sbus_bus self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus) self.submodules.sbus_bus_stat = SBusFPGABusStat(soc=self, sbus_bus=self.sbus_bus) self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys) if (usb): if (single_dvma_master): self.comb += self.usb_host.wb_dma.connect( self.wishbone_slave_sys) if (sdcard): self.add_sdcard() #pad_sdcard_interrupt = platform.get_irq(irq_req=2, device="sdcard", next_down=True, next_up=False) #if (pad_sdcard_interrupt is None): # print(" ***** ERROR ***** sdcard requires an interrupt") # assert(False) #sig_sdcard_interrupt = Signal(reset=1) ## the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt) #self.comb += pad_sdcard_interrupt.eq(sig_sdcard_interrupt) #self.comb += sig_sdcard_interrupt.eq(~self.sdirq.irq) ## if (usb or engine or sdcard): if (not single_dvma_master): self.bus.add_slave(name="dvma_bridge", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get( "dvma_bridge", None), size=0x03ffffff, cached=False)) if (trng): self.submodules.trng = NeoRV32TrngWrapper(platform=platform) # beware the naming, as 'clk50' 'sysclk' 'clk200' are used in the original platform constraints # the local engine.py was slightly modified to have configurable names, so we can have 'clk50', 'clk100', 'clk200' # Beware that Engine implicitely runs in 'sys' by default, need to rename that one as well # Actually renaming 'sys' doesn't work - unless we can CDC the CSRs as well if (engine): self.submodules.curve25519engine = ClockDomainsRenamer({ "eng_clk": "clk50", "rf_clk": "clk200", "mul_clk": "clk100_gated" })(Engine(platform=platform, prefix=self.mem_map.get("curve25519engine", None))) # , "sys":"clk100" self.bus.add_slave( "curve25519engine", self.curve25519engine.bus, SoCRegion(origin=self.mem_map.get("curve25519engine", None), size=0x20000, cached=False)) if (not single_dvma_master): self.bus.add_master(name="curve25519engineLS", master=self.curve25519engine.busls) else: self.comb += self.curve25519engine.busls.connect( self.wishbone_slave_sys) self.comb += self.crg.curve25519_on.eq( self.curve25519engine.power.fields.on) if (i2c): self.submodules.i2c = i2c.RTLI2C(platform, pads=platform.request("i2c")) if (framebuffer): self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if (bw2): self.submodules.bw2 = bw2_fb.bw2( soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga" ) # clock_domain for the VGA side, bw2 is running in cd_sys self.bus.add_slave("bw2_bt", self.bw2.bus, SoCRegion(origin=self.mem_map.get( "cg3_bt", None), size=0x1000, cached=False)) # bw2 uses cg3_bt elif (cg3): self.submodules.cg3 = cg3_fb.cg3( soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga" ) # clock_domain for the VGA side, cg3 is running in cd_sys self.bus.add_slave( "cg3_bt", self.cg3.bus, SoCRegion(origin=self.mem_map.get("cg3_bt", None), size=0x1000, cached=False)) else: self.submodules.cg6 = cg6_fb.cg6( soc=self, phy=self.videophy, timings=cg3_res, clock_domain="vga" ) # clock_domain for the VGA side, cg6 is running in cd_sys self.bus.add_slave( "cg6_bt", self.cg6.bus, SoCRegion(origin=self.mem_map.get("cg6_bt", None), size=0x1000, cached=False)) if (cg6): self.submodules.cg6_accel = cg6_accel.CG6Accel(soc=self, base_fb=base_fb, hres=hres, vres=vres) self.bus.add_slave( "cg6_fbc", self.cg6_accel.bus, SoCRegion(origin=self.mem_map.get("cg6_fbc", None), size=0x2000, cached=False)) self.bus.add_slave( "cg6_fhc", self.cg6.bus2, SoCRegion(origin=self.mem_map.get("cg6_fhc", None), size=0x2000, cached=False)) self.bus.add_slave( "cg6_alt", self.cg6.bus3, SoCRegion(origin=self.mem_map.get("cg6_alt", None), size=0x2000, cached=False)) self.bus.add_master(name="cg6_accel_r5_i", master=self.cg6_accel.ibus) self.bus.add_master(name="cg6_accel_r5_d", master=self.cg6_accel.dbus) cg6_rom_file = "blit.raw" cg6_rom_data = soc_core.get_mem_data(cg6_rom_file, "little") self.add_ram("cg6_accel_rom", origin=self.mem_map["cg6_accel_rom"], size=2**13, contents=cg6_rom_data, mode="r") self.add_ram("cg6_accel_ram", origin=self.mem_map["cg6_accel_ram"], size=2**12, mode="rw") print("IRQ to Device map:\n") print(platform.irq_device_map) print("Device to IRQ map:\n") print(platform.device_irq_map) #disable remaining IRQs if (version == "V1.0"): platform.avail_irqs.add(7) for irq in platform.avail_irqs: pad_int = platform.request(f"SBUS_3V3_INT{irq}s") oe_int = Signal(reset=0) val_int = Signal(reset=1) self.specials += Tristate(pad_int, val_int, oe_int, None)
def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, **kwargs): platform = sds1104xe.Platform() # SoCCore ---------------------------------------------------------------------------------- if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "crossover" # Defaults to Crossover UART. SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Siglent SDS1104X-E", **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_etherbone) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY( pads=PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]), memtype="DDR3", nphases=4, sys_clk_freq=sys_clk_freq) self.add_sdram("sdram", phy=self.ddrphy, module=MT41K64M16(sys_clk_freq, "1:4"), l2_cache_size=kwargs.get("l2_size", 8192)) # Etherbone -------------------------------------------------------------------------------- if with_etherbone: # FIXME: Simplify LiteEth Hybrid MAC integration. from liteeth.common import convert_ip from liteeth.mac import LiteEthMAC from liteeth.core.arp import LiteEthARP from liteeth.core.ip import LiteEthIP from liteeth.core.udp import LiteEthUDP from liteeth.core.icmp import LiteEthICMP from liteeth.core import LiteEthUDPIPCore from liteeth.frontend.etherbone import LiteEthEtherbone # Ethernet PHY self.submodules.ethphy = LiteEthPHYMII( clock_pads=self.platform.request("eth_clocks"), pads=self.platform.request("eth")) etherbone_ip_address = convert_ip("192.168.1.51") etherbone_mac_address = 0x10e2d5000001 # Ethernet MAC self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8, interface="hybrid", endianness=self.cpu.endianness, hw_mac=etherbone_mac_address) # Software Interface. self.add_memory_region("ethmac", getattr(self.mem_map, "ethmac", None), 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # Hardware Interface. self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8) self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8) self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8) self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8) self.add_constant( "ETH_PHY_NO_RESET" ) # Disable reset from BIOS to avoid disabling Hardware Interface. # Etherbone self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master") self.add_wb_master(self.etherbone.wishbone.bus) # Timing constraints eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk self.platform.add_period_constraint(eth_rx_clk, 1e9 / self.ethphy.rx_clk_freq) self.platform.add_period_constraint(eth_tx_clk, 1e9 / self.ethphy.tx_clk_freq) self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) # Video ------------------------------------------------------------------------------------ video_timings = ("800x480@60Hz", { "pix_clk": 33.3e6, "h_active": 800, "h_blanking": 256, "h_sync_offset": 210, "h_sync_width": 1, "v_active": 480, "v_blanking": 45, "v_sync_offset": 22, "v_sync_width": 1, }) if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("lcd"), clock_domain="dvi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings=video_timings, clock_domain="dvi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings=video_timings, clock_domain="dvi")
def __init__(self, sys_clk_freq=int(50e6), revision="revd", sdram_rate="1:2", mister_sdram=None, with_video_terminal=False, **kwargs): platform = terasic_sockit.Platform(revision) # Defaults to UART over JTAG because serial is attached to the HPS and cannot be used. if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "jtag_atlantic" # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on the Terasic SoCKit", ident_version=True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if mister_sdram == "xs_v22": sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy=self.sdrphy, module=W9825G6KH6(sys_clk_freq, sdram_rate), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) if mister_sdram == "xs_v24": sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy=self.sdrphy, module=AS4C32M16(sys_clk_freq, sdram_rate), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True) # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: vga_pads = platform.request("vga") self.comb += [vga_pads.sync_n.eq(0), vga_pads.blank_n.eq(1)] self.specials += DDROutput(i1=1, i2=0, o=vga_pads.clk, clk=ClockSignal("vga")) self.submodules.videophy = VideoVGAPHY(vga_pads, clock_domain="vga") self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser(pads=platform.request_all("user_led"), sys_clk_freq=sys_clk_freq)
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, with_jtagbone=True, with_spi_flash=False, **kwargs): platform = qmtech_xc7a35t.Platform(toolchain=toolchain, with_daughterboard=with_daughterboard) # SoCCore ---------------------------------------------------------------------------------- if (kwargs["uart_name"] == "serial") and (not with_daughterboard): kwargs["uart_name"] = "gpio_serial" SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on QMTech XC7A35T" + (" + Daughterboard" if with_daughterboard else ""), **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, sys_clk_freq = sys_clk_freq) self.add_sdram("sdram", phy = self.ddrphy, module = MT41J128M16(sys_clk_freq, "1:4"), l2_cache_size = kwargs.get("l2_size", 8192) ) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) if with_ethernet: self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # The daughterboard has the tx clock wired to a non-clock pin, so we can't help it self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]") # Jtagbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import MT25QL128 from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=MT25QL128(Codes.READ_1_1_1), with_master=True) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) if not with_daughterboard and kwargs["uart_name"] == "serial": kwargs["uart_name"] = "jtag_serial"