def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Nano 4K")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq",
default=27e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash",
ext=".fs")) # FIXME
prog.flash(0, builder.get_bios_filename(), external=True)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on Efinix Trion T20 MIPI Dev Kit")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_spi_flash=args.with_spi_flash,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on Spartan Edge Accelerator")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
target_group.add_argument("--with-jtagbone",
action="store_true",
help="Enable Jtagbone support.")
target_group.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Colorbars (HDMI).")
target_group.add_argument("--with-neopixel",
action="store_true",
help="Enable onboard 2 Neopixels Leds.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_jtagbone=args.with_jtagbone,
with_video_terminal=args.with_video_terminal,
with_neopixel=args.with_neopixel,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Hackaday Badge")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq",
default=48e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on Lattice iCE40UP5k EVN breakout board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--sys-clk-freq",
default=12e6,
help="System clock frequency.")
target_group.add_argument("--bios-flash-offset",
default="0x20000",
help="BIOS offset in SPI Flash.")
target_group.add_argument("--flash",
action="store_true",
help="Flash Bitstream.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(bios_flash_offset=int(args.bios_flash_offset, 0),
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.flash:
flash(args.bios_flash_offset)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Jungle Electronics FireAnt")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0x40000", help="BIOS offset in SPI Flash.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".hex")) # FIXME
prog.flash(args.bios_flash_offset, builder.get_bios_filename())
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on BerkeleyLab Marble")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
target_group.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--with-rts-reset", action="store_true", help="Connect UART RTS line to sys_clk reset.")
target_group.add_argument("--with-bist", action="store_true", help="Add DDR3 BIST Generator/Checker.")
target_group.add_argument("--spd-dump", type=str, help="DDR3 configuration file, dumped using the `spdread` command in LiteX BIOS.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
with_bist = args.with_bist,
spd_dump = args.spd_dump,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on the Terasic SoCKit")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--single-rate-sdram", action="store_true", help="Clock SDRAM with 1x the sytem clock (instead of 2x).")
target_group.add_argument("--mister-sdram-xs-v22", action="store_true", help="Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card.")
target_group.add_argument("--mister-sdram-xs-v24", action="store_true", help="Use optional MiSTer SDRAM module XS v2.4 on J2 on GPIO daughter card.")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--revision", default="revd", help="Board revision (revb, revc or revd).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
revision = args.revision,
sdram_rate = "1:1" if args.single_rate_sdram else "1:2",
mister_sdram = "xs_v22" if args.mister_sdram_xs_v22 else "xs_v24" if args.mister_sdram_xs_v24 else None,
with_video_terminal = args.with_video_terminal,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Atlys")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
target_group.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on FPC-III")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Cam Link 4K")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=81e6,
help="System clock frequency.")
target_group.add_argument("--toolchain",
default="trellis",
help="FPGA toolchain (trellis or diamond).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
toolchain=args.toolchain,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(
args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Alchitry Au(+)")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--variant", default="au", help="Board variant (au or au+).")
target_group.add_argument("--sys-clk-freq", default=83333333, help="System clock frequency.")
target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
variant = args.variant,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_spi_flash = args.with_spi_flash,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on iCEBreaker")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream and BIOS.")
target_group.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.")
target_group.add_argument("--bios-flash-offset", default="0xa0000", help="BIOS offset in SPI Flash.")
target_group.add_argument("--revision", default="v1", help="Board revision (v0 or v1).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)),
revision = args.revision,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.flash:
from litex.build.dfu import DFUProg
prog_gw = DFUProg(vid="1d50", pid="0x6146", alt=0)
prog_sw = DFUProg(vid="1d50", pid="0x6146", alt=1)
prog_gw.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".bin"), reset=False) # FIXME
prog_sw.load_bitstream(builder.get_bios_filename())
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE0-Nano")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency.")
target_group.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
sdram_rate=args.sdram_rate,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="radiant", help="FPGA toolchain (radiant or prjoxide).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
target_group.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip (none, 0 or 1).")
target_group.add_argument("--prog-target", default="direct", help="Programming Target (direct or flash).")
builder_args(parser)
soc_core_args(parser)
oxide_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
hyperram = args.with_hyperram,
toolchain = args.toolchain,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.prog_target)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
# Arguments.
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX standalone SoC generator")
target_group = parser.add_argument_group(title="Generator options")
target_group.add_argument("--name", default="litex_soc", help="SoC Name.")
target_group.add_argument("--build",
action="store_true",
help="Build SoC.")
target_group.add_argument("--sys-clk-freq",
default=int(50e6),
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# SoC.
soc = LiteXSoCGenerator(name=args.name,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
# Build.
builder = Builder(soc, **builder_argdict(args))
builder.build(build_name=args.name, run=args.build)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Arty Z7")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--variant", default="z7-20", help="Board variant (z7-20 or z7-10).")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
parser.set_defaults(cpu_type="zynq7000")
parser.set_defaults(no_uart=True)
args = parser.parse_args()
soc = BaseSoC(
variant = args.variant,
toolchain = args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Pano Logic G2")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--revision", default="c", help="Board revision (b or c).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
revision = args.revision,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on ZCU216")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
parser.set_defaults(cpu_type="zynqmp")
parser.set_defaults(no_uart=True)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
if args.cpu_type == "zynqmp":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on DE10-Lite")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency.")
target_group.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_video_terminal=args.with_video_terminal,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on EBAZ4205")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"),
device=1)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC Blackmagic Decklink Intensity Pro 4K")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie | True, # FIXME: Always enable PCIe for now.
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on ECP5 Evaluation Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream")
target_group.add_argument(
"--toolchain",
default="trellis",
help="FPGA toolchain: trellis (default) or diamond")
target_group.add_argument("--sys-clk-freq",
default=60e6,
help="System clock frequency (default: 60MHz)")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Alveo U280")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=150e6,
help="System clock frequency."
) # HBM2 with 250MHz, DDR4 with 150MHz (1:4)
target_group.add_argument(
"--ddram-channel", default="0",
help="DDRAM channel (0, 1, 2 or 3).") # also selects clk 0 or 1
target_group.add_argument("--with-pcie",
action="store_true",
help="Enable PCIe support.")
target_group.add_argument("--driver",
action="store_true",
help="Generate PCIe driver.")
target_group.add_argument("--with-hbm",
action="store_true",
help="Use HBM2.")
target_group.add_argument("--with-analyzer",
action="store_true",
help="Enable Analyzer.")
target_group.add_argument("--with-led-chaser",
action="store_true",
help="Enable LED Chaser.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
if args.with_hbm:
args.sys_clk_freq = 250e6
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
ddram_channel=int(args.ddram_channel, 0),
with_pcie=args.with_pcie,
with_led_chaser=args.with_led_chaser,
with_hbm=args.with_hbm,
with_analyzer=args.with_analyzer,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on NeTV2")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--variant",
default="a7-35",
help="Board variant (a7-35 or a7-100).")
target_group.add_argument("--sys-clk-freq",
default=100e6,
help="System clock frequency.")
target_group.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
target_group.add_argument("--with-pcie",
action="store_true",
help="Enable PCIe support.")
target_group.add_argument("--driver",
action="store_true",
help="Generate PCIe driver.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(variant=args.variant,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_pcie=args.with_pcie,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(
description="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq",
default=200e6,
help="System clock frequency.")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
target_group.add_argument("--with-hyperram",
action="store_true",
help="Enable HyperRAM.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_spi_flash=args.with_spi_flash,
with_hyperram=args.with_hyperram,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
from litex.build.openfpgaloader import OpenFPGALoader
prog = OpenFPGALoader("titanium_ti60_f225")
prog.flash(0, builder.get_bitstream_filename(mode="flash",
ext=".hex")) # FIXME
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Nexys4")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=75e6,
help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal",
action="store_true",
help="Enable Video Terminal (VGA).")
viopts.add_argument("--with-video-framebuffer",
action="store_true",
help="Enable Video Framebuffer (VGA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_video_terminal=args.with_video_terminal,
with_video_framebuffer=args.with_video_framebuffer,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Tang Nano 9K")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--flash",
action="store_true",
help="Flash Bitstream.")
target_group.add_argument("--sys-clk-freq",
default=27e6,
help="System clock frequency.")
target_group.add_argument("--bios-flash-offset",
default="0x0",
help="BIOS offset in SPI Flash.")
target_group.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
target_group.add_argument(
"--prog-kit",
default="openfpgaloader",
help="Programmer select from Gowin/openFPGALoader.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
bios_flash_offset=int(args.bios_flash_offset, 0),
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer(kit=args.prog_kit)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer(kit=args.prog_kit)
prog.flash(0, builder.get_bitstream_filename(mode="flash",
ext=".fs")) # FIXME
# Axternal SPI programming not supported by gowin 'programmer_cli' now!
# if needed, use openFPGALoader or Gowin programmer GUI
if args.prog_kit == "openfpgaloader":
prog.flash(int(args.bios_flash_offset, 0),
builder.get_bios_filename(),
external=True)
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on KCU105")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=125e6,
help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support.")
target_group.add_argument("--eth-ip",
default="192.168.1.50",
help="Ethernet/Etherbone IP address.")
target_group.add_argument("--with-pcie",
action="store_true",
help="Enable PCIe support.")
target_group.add_argument("--driver",
action="store_true",
help="Generate PCIe driver.")
target_group.add_argument("--with-sata",
action="store_true",
help="Enable SATA support (over SFP2SATA).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_ip=args.eth_ip,
with_pcie=args.with_pcie,
with_sata=args.with_sata,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc,
os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH 10CL006")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build",
action="store_true",
help="Build bitstream.")
target_group.add_argument("--load",
action="store_true",
help="Load bitstream.")
target_group.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency.")
target_group.add_argument(
"--sdram-rate",
default="1:2",
help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
target_group.add_argument(
"--with-daughterboard",
action="store_true",
help="Board plugged into the QMTech daughterboard.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard",
action="store_true",
help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support.")
target_group.add_argument("--with-spi-flash",
action="store_true",
help="Enable SPI Flash (MMAPed).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_daughterboard=args.with_daughterboard,
with_spi_flash=args.with_spi_flash,
sdram_rate=args.sdram_rate,
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
