def main():
parser = argparse.ArgumentParser(description="LiteX SoC on MarbleMini")
builder_args(parser)
# soc_sdram_args(parser)
soc_core_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy",
default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p",
"--program-only",
action="store_true",
help="select Ethernet PHY (rgmii or 1000basex)")
args = parser.parse_args()
if args.with_ethernet:
soc = LTCSocDev(phy=args.ethernet_phy, **soc_core_argdict(args))
# soc = EthernetSoC(phy=args.ethernet_phy, **soc_sdram_argdict(args))
# soc = EthernetSoC(phy=args.ethernet_phy, **soc_core_argdict(args))
else:
soc = BaseSoC(**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
if not args.program_only:
vns = builder.build()
if False:
soc.analyzer.do_exit(vns)
prog = soc.platform.create_programmer()
import os
prog.load_bitstream(os.path.join(builder.gateware_dir, "marblemini.bit"))
def main():
parser = argparse.ArgumentParser(description="SDRAM Loopback SoC on Marble*")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--ip", default="192.168.19.70",
help="Assign an ip address")
parser.add_argument("--ethernet-phy", default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p", "--program-only", action="store_true",
help="Don't build, just program the existing bitfile")
parser.add_argument("--build", action="store_true",
help="Build FPGA bitstream")
parser.add_argument("--load", action="store_true",
help="program FPGA")
parser.add_argument("--threads", default=4,
help="set number of threads (default=4)")
parser.add_argument("--trace", action="store_true",
help="enable VCD tracing")
parser.add_argument("-s", "--sim", action="store_true",
help="Simulate")
args = parser.parse_args()
if args.sim:
soc_kwargs = soc_core_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
soc_kwargs["integrated_main_ram_size"] = 0x10000
soc_kwargs = soc_core_argdict(args)
soc_kwargs["uart_name"] = "sim"
# sim_config.add_module("serial2console", "serial")
sim_config.add_module(
'ethernet',
"eth",
args={"interface": "xxx1",
"ip": "192.168.88.101",
"vcd_name": "foo.vcd"})
soc = SDRAMSimSoC(phy="rgmii",
with_ethernet=True,
with_etherbone=True,
with_sdram=True,
etherbone_ip_address="192.168.88.50",
etherbone_mac_address=0x12345678abcd,
**soc_kwargs)
builder = Builder(soc, **builder_argdict(args))
# discard result, or save in vns?
builder.build(
threads=args.threads,
trace=args.trace,
sim_config=sim_config)
kwargs = soc_core_argdict(args)
# soc = SDRAMLoopbackSoC(ip=args.ip, phy=args.ethernet_phy, **kwargs)
soc = SDRAMDevSoC(ip=args.ip, phy=args.ethernet_phy, **kwargs)
builder = Builder(soc, **builder_argdict(args))
builder.build()
if args.load:
prog = marble.Platform().create_programmer()
prog.load_bitstream(os.path.join("build", "marble", "gateware", "marble.bit"))
def main():
parser = argparse.ArgumentParser(description="Datapipe simulation SoC*")
builder_args(parser)
soc_core_args(parser)
# soc_core_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy",
default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p",
"--program-only",
action="store_true",
help="Don't build, just program the existing bitfile")
parser.add_argument("--build",
action="store_true",
help="Build FPGA bitstream")
parser.add_argument("--load", action="store_true", help="program FPGA")
parser.add_argument("--threads",
default=4,
help="set number of threads (default=4)")
parser.add_argument("--trace",
action="store_true",
help="enable VCD tracing")
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
soc_kwargs["integrated_main_ram_size"] = 0x10000
soc_kwargs = soc_core_argdict(args)
soc_kwargs["uart_name"] = "sim"
# sim_config.add_module("serial2console", "serial")
sim_config.add_module('ethernet',
"eth",
args={
"interface": "xxx1",
"ip": "192.168.88.101",
"vcd_name": "foo.vcd"
})
soc = SDRAMSimSoC(phy="rgmii",
with_ethernet=True,
with_etherbone=True,
with_sdram=True,
etherbone_ip_address="192.168.88.50",
etherbone_mac_address=0x12345678abcd,
**soc_kwargs)
builder = Builder(soc, **builder_argdict(args))
# discard result, or save in vns?
builder.build(threads=args.threads,
trace=args.trace,
sim_config=sim_config)
def make_soc(self, **kwargs) -> litex_soc.LiteXSoC:
"""Utilizes self.soc_constructor to make a LiteXSoC.
Args:
**kwargs: Arguments meant to extend/overwrite the general
arguments to self.soc_constructor.
Returns:
The LiteXSoC for the target board.
"""
base_soc_kwargs = {
'with_ethernet': self.args.with_ethernet,
'with_etherbone': self.args.with_etherbone,
'with_mapped_flash': self.args.with_mapped_flash,
'with_spi_sdcard': self.args.with_spi_sdcard,
'with_video_framebuffer': self.args.with_video_framebuffer,
}
base_soc_kwargs.update(soc_core.soc_core_argdict(self.args))
if self.args.toolchain:
base_soc_kwargs['toolchain'] = self.args.toolchain
if self.args.sys_clk_freq:
base_soc_kwargs['sys_clk_freq'] = self.args.sys_clk_freq
print("make_soc: cpu_variant is", self.args.cpu_variant)
build_cpu_variant_if_needed(self.args.cpu_variant)
base_soc_kwargs.update(kwargs)
return self.soc_constructor(**base_soc_kwargs)
def get_soc_kwargs(args):
soc_kwargs = soc_core_argdict(args)
# Set some defaults for SoC - no CPU, memory, etc.
soc_kwargs.update(
dict(
cpu_type="vexriscv",
cpu_variant="minimal",
no_timer=False,
no_ctrl=False,
no_uart=False,
uart_name="crossover",
integrated_rom_size=0x10000, # Litex will shrink this to fit BIOS
integrated_sram_size=0x2000,
integrated_main_ram_size=0,
))
# Common arguments to Rowhammer SoC
module = get_sdram_module(args.module) if args.from_spd is None else None
soc_kwargs.update(
dict(
args=args,
sys_clk_freq=int(float(args.sys_clk_freq)),
sdram_module_cls=module,
sdram_module_speedgrade=args.speedgrade,
sdram_module_spd_file=args.from_spd,
ip_address=args.ip_address,
mac_address=int(args.mac_address, 0),
udp_port=int(args.udp_port, 0),
))
return soc_kwargs
def get_soc_kwargs(args):
soc_kwargs = soc_core_argdict(args)
# Set some defaults for SoC - no CPU, memory, etc.
soc_kwargs.update(
dict(
cpu_type="vexriscv",
cpu_variant="minimal",
no_timer=False,
no_ctrl=False,
no_uart=False,
uart_name="crossover",
integrated_rom_size=0x8000,
integrated_sram_size=0x2000,
integrated_main_ram_size=0,
))
# Common arguments to row hammer SoC
soc_kwargs.update(
dict(
args=args,
sys_clk_freq=int(float(args.sys_clk_freq)),
ip_address=args.ip_address,
mac_address=int(args.mac_address, 0),
udp_port=int(args.udp_port, 0),
))
return soc_kwargs
def main():
parser = argparse.ArgumentParser(
description="SDRAM Loopback SoC on Marble*")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy",
default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p",
"--program-only",
action="store_true",
help="Don't build, just program the existing bitfile")
parser.add_argument("--build",
action="store_true",
help="Build FPGA bitstream")
parser.add_argument("--load", action="store_true", help="program FPGA")
args = parser.parse_args()
if args.build:
soc = SDRAMLoopbackSoC(with_ethernet=args.with_ethernet,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
# discard result, or save in vns?
builder.build(run=not args.program_only)
if args.load:
prog = kc705.Platform().create_programmer()
prog.load_bitstream(
os.path.join("build", "kc705", "gateware", "kc705.bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--sys-clk-freq", type=float, default=48e6, help="Select system clock frequency")
parser.add_argument("--document-only", action="store_true", help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash", action="store_true", help="Load bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(sys_clk_freq=int(args.sys_clk_freq), **soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../litex-pac/soc.svd"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
# If requested load the resulting bitstream onto the iCEBreaker
if args.flash:
IceStormProgrammer().flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Leech")
parser.add_argument("--sys-clk-freq",
type=float,
default=48e6,
help="Select system clock frequency")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(sys_clk_freq=int(args.sys_clk_freq),
**soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software: we don't have CPU.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../litex-pac/soc.svd"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
def main():
parser = argparse.ArgumentParser(
description="Build test file for dummy or eptri module")
builder_args(parser)
soc_core_args(parser)
parser.add_argument('--dir',
metavar='DIRECTORY',
default='build',
help='Output directory (defauilt: %(default)s)')
parser.add_argument('--csr',
metavar='CSR',
default='csr.csv',
help='csr file (default: %(default)s)')
parser.add_argument("--rom-init", default=None, help="rom_init file")
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
if args.rom_init is not None:
soc_kwargs["integrated_rom_init"] = \
get_mem_data(args.rom_init, endianness='little')
output_dir = args.dir
platform = Platform()
soc = BaseSoC(platform, **soc_kwargs)
builder = Builder(soc,
output_dir=output_dir,
csr_csv=args.csr,
compile_software=False)
vns = builder.build(run=False)
soc.do_exit(vns)
print("""Simulation build complete. Output files:
{}/gateware/dut.v Source Verilog file. Run this under Cocotb.
""".format(output_dir))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
cls = BaseSoC
soc = cls(**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on TinyFPGA_BX")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--seed", default=0, help="Seed to use in Nextpnr")
parser.add_argument("--placer", default="heap", choices=["sa", "heap"], help="Which placer to use in Nextpnr")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed, debug=True, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--flash-offset",
default=0x40000,
help="Boot offset in SPI Flash")
parser.add_argument("--sys-clk-freq",
type=float,
default=21e6,
help="Select system clock frequency")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash", action="store_true", help="Load bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(flash_offset=args.flash_offset,
sys_clk_freq=int(args.sys_clk_freq),
**soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../litex-pac/soc.svd"
if builder_kwargs["memory_x"] is None:
builder_kwargs["memory_x"] = "../litex-pac/memory.x"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="iCEBreaker LiteX RISC-V Example SOC",
author="Piotr Esden-Tempski")
# If requested load the resulting bitstream onto the iCEBreaker
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
def main():
parser = argparse.ArgumentParser(
description=__doc__, formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq",
default=125e6,
help="System clock frequency (default: 125MHz)")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--with-rts-reset",
action="store_true",
help="Connect UART RTS line to sys_clk reset")
parser.add_argument("--with-bist",
action="store_true",
help="Add DDR3 BIST Generator/Checker")
parser.add_argument(
"--spd-dump",
type=str,
help=
"DDR3 configuration file, dumped using the `spdread` command in LiteX BIOS"
)
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_bist=args.with_bist,
spd_dump=args.spd_dump,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--build-name", default="top", help="Build name")
parser.add_argument(
"--toolchain",
default="vivado",
help="Gateware toolchain to use, vivado or symbiflow (default)")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-ram",
action="store_true",
help="Enable Main RAM")
parser.add_argument("--board",
default="a7-35",
help="Specifies Arty Board version")
parser.add_argument("--builddir", help="Build directory")
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
if args.board not in ["a7-35", "a7-100"]:
raise ValueError("Unsupported device variant!")
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq=int(60e6),
with_ethernet=args.with_ethernet,
with_ram=args.with_ram,
board_variant=args.board,
**soc_core_argdict(args))
builder = Builder(soc, output_dir=args.builddir)
builder_kwargs = vivado_build_argdict(
args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build, build_name=args.build_name)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
soc_cls = BaseSoC
cpu = VexRiscv
parser = argparse.ArgumentParser(description="LiteX SoC")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--build_gateware", action='store_true')
parser.add_argument("--yosys", action="store_true")
parser.add_argument("--sim", action="store_true")
parser.add_argument("--run", action="store_true")
args = parser.parse_args()
builder_kwargs = builder_argdict(args)
soc_kwargs = soc_core_argdict(args)
platform = sim_platform2.Platform() if args.sim else platform1.Platform()
output_dir = builder_kwargs['output_dir'] = 'build'
fw_file = os.path.join(output_dir, "software", "firmware", "firmware.bin")
soc_kwargs['integrated_rom_size'] = 32 * 1024
soc_kwargs["integrated_main_ram_size"] = 16 * 1024
try:
soc_kwargs['integrated_main_ram_init'] = get_mem_data(
fw_file, cpu.endianness)
except OSError:
pass
soc = BaseSoC(platform,
cpu=cpu,
sim=args.sim,
output_dir=output_dir,
**soc_kwargs)
builder = Builder(soc, **builder_kwargs)
builder.add_software_package("firmware",
src_dir=os.path.join(os.getcwd(), 'src',
'firmware'))
if args.sim:
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
builder.build(run=False, sim_config=sim_config, opt_level='O3')
if args.run:
builder.build(build=False, sim_config=sim_config)
else:
builder.build(run=args.build_gateware,
synth_mode="yosys" if args.yosys else "vivado")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
parser.add_argument(
"--board", choices=["evt", "pvt", "hacker"], required=True,
help="build for a particular hardware board"
)
parser.add_argument(
"--seed", default=0, help="seed to use in nextpnr"
)
parser.add_argument(
"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
)
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board, pnr_placer=args.placer, pnr_seed=args.seed,
debug=True, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--nextpnr-seed",
default=0,
help="Select nextpnr pseudo random seed")
parser.add_argument("--nextpnr-placer",
default="heap",
choices=["sa", "heap"],
help="Select nextpnr placer algorithm")
parser.add_argument(
"--debug",
action="store_true",
help=
"Enable debug features. (UART has to be used with the wishbone-tool.)")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(debug=args.debug, **soc_core_argdict(args))
soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed,
nextpnr_placer=args.nextpnr_placer)
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
builder = Builder(soc, **builder_kwargs)
vns = builder.build()
soc.do_exit(vns)
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="iCEBreaker LiteX Riscv Example SOC",
author="Piotr Esden-Tempski")
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
builder_args(parser.add_argument_group(title="Builder"))
soc_core_args(parser.add_argument_group(title="SoC Core"))
group = parser.add_argument_group(title="LPDDR4 simulation")
group.add_argument("--sdram-verbosity",
default=0,
help="Set SDRAM checker verbosity")
group.add_argument("--trace", action="store_true", help="Enable Tracing")
group.add_argument("--trace-fst",
action="store_true",
help="Enable FST tracing (default=VCD)")
group.add_argument("--trace-start",
default=0,
help="Cycle to start tracing")
group.add_argument("--trace-end", default=-1, help="Cycle to end tracing")
group.add_argument("--trace-reset",
default=0,
help="Initial traceing state")
group.add_argument("--sys-clk-freq",
default="50e6",
help="Core clock frequency")
group.add_argument("--auto-precharge",
action="store_true",
help="Use DRAM auto precharge")
group.add_argument("--no-refresh",
action="store_true",
help="Disable DRAM refresher")
group.add_argument("--log-level",
default="all=INFO",
help="Set simulation logging level")
group.add_argument("--disable-delay",
action="store_true",
help="Disable CPU delays")
group.add_argument("--gtkw-savefile",
action="store_true",
help="Generate GTKWave savefile")
group.add_argument("--no-masked-write",
action="store_true",
help="Use LPDDR4 WRITE instead of MASKED-WRITE")
group.add_argument("--no-run",
action="store_true",
help="Don't run the simulation, just generate files")
group.add_argument("--double-rate-phy",
action="store_true",
help="Use sim PHY with 2-stage serialization")
group.add_argument("--finish-after-memtest",
action="store_true",
help="Stop simulation after DRAM memory test")
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig()
sys_clk_freq = int(float(args.sys_clk_freq))
clocks = get_clocks(sys_clk_freq)
clocks.add_clockers(sim_config)
# Configuration --------------------------------------------------------------------------------
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
args.with_sdram = True
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(clocks=clocks,
auto_precharge=args.auto_precharge,
with_refresh=not args.no_refresh,
trace_reset=int(args.trace_reset),
log_level=args.log_level,
disable_delay=args.disable_delay,
masked_write=not args.no_masked_write,
double_rate_phy=args.double_rate_phy,
finish_after_memtest=args.finish_after_memtest,
**soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
build_kwargs = dict(sim_config=sim_config,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
vns = builder.build(run=False, **build_kwargs)
if args.gtkw_savefile:
generate_gtkw_savefile(builder, vns, trace_fst=args.trace_fst)
if not args.no_run:
builder.build(build=False, **build_kwargs)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--flash-offset",
default=0x40000,
help="Boot offset in SPI Flash")
parser.add_argument("--sys-clk-freq",
type=float,
default=21e6,
help="Select system clock frequency")
parser.add_argument("--nextpnr-seed",
default=0,
help="Select nextpnr pseudo random seed")
parser.add_argument("--nextpnr-placer",
default="heap",
choices=["sa", "heap"],
help="Select nextpnr placer algorithm")
parser.add_argument(
"--debug",
action="store_true",
help=
"Enable debug features. (UART has to be used with the wishbone-tool.)")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash", action="store_true", help="Load bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(debug=args.debug,
flash_offset=args.flash_offset,
sys_clk_freq=int(args.sys_clk_freq),
**soc_core_argdict(args))
soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed,
nextpnr_placer=args.nextpnr_placer)
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../rust/icebesoc-pac/iCEBESOC.svd"
if builder_kwargs["memory_x"] is None:
builder_kwargs["memory_x"] = "../rust/icebesoc-pac/memory.x"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="iCEBreaker LiteX Riscv Example SOC",
author="Piotr Esden-Tempski")
# If requested load the resulting bitstream onto the iCEBreaker
if args.flash:
IceStormProgrammer().flash(0x00000000,
"soc_basesoc_icebreaker/gateware/top.bin")
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on Colorlight 5A-75X")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--flash-offset",
default=0x100000,
help="Boot offset in SPI Flash")
parser.add_argument("--sys-clk-freq",
type=float,
default=50e6,
help="Select system clock frequency")
parser.add_argument(
"--debug",
action="store_true",
help=
"Enable debug features. (UART has to be used with the wishbone-tool.)")
parser.add_argument("--board",
default="5a-75b",
help="Board type: 5a-75b (default) or 5a-75e")
parser.add_argument("--revision",
default="7.0",
type=str,
help="Board revision 7.0 (default), 6.0 or 6.1")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--eth-phy",
default=0,
type=int,
help="Ethernet PHY 0 or 1 (default=0)")
parser.add_argument("--use-internal-osc",
action="store_true",
help="Use internal oscillator")
parser.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash",
action="store_true",
help="Load bitstream to flash")
parser.add_argument("--load",
action="store_true",
help="Load bitstream to SRAM")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
# Create the SOC
soc = BaseSoC(board=args.board,
revision=args.revision,
debug=args.debug,
flash_offset=args.flash_offset,
sys_clk_freq=int(args.sys_clk_freq),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_phy=args.eth_phy,
use_internal_osc=args.use_internal_osc,
sdram_rate=args.sdram_rate,
**soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../rust/litex-pac/clSOC.svd"
if builder_kwargs["memory_x"] is None:
builder_kwargs["memory_x"] = "../rust/litex-pac/memory.x"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build(**trellis_argdict(args), run=args.build)
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="Colorlight 5A-75x LiteX Riscv SOC",
author="DerFetzer")
modify_memory_x(builder_kwargs)
modify_svd(builder_kwargs)
# If requested load the resulting bitstream onto the 5A-75X
if args.flash or args.load:
prog = ECP5Programmer()
if args.load:
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if args.flash:
prog.flash(
0x00000000,
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
patch_cpu_variant()
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--sim-trace",
action="store_true",
help="Whether to enable tracing of simulation")
parser.add_argument("--sim-trace-start",
default=0,
help="Start tracing at this time in picoseconds")
parser.add_argument("--sim-trace-end",
default=-1,
help="Stop tracing at this time in picoseconds")
parser.add_argument("--run",
action="store_true",
help="Whether to run the simulation")
parser.add_argument("--separate-arena",
action="store_true",
help="Add arena mem region at 0x60000000")
parser.add_argument("--cfu-mport", action="store_true", help="Add ports between arena and CFU " \
"(implies --separate-arena)")
parser.add_argument("--bin",
help="RISCV binary to run. Required if --run is set.")
parser.set_defaults(csr_csv='csr.csv',
uart_name='serial',
uart_baudrate=921600,
cpu_variant='full+cfu+debug',
with_etherbone=False)
args = parser.parse_args()
bin = None
if args.run:
if args.bin:
bin = get_mem_data(args.bin, "little")
else:
print("must provide --bin if using --run")
# cfu_mport implies separate_arena
if args.cfu_mport:
args.separate_arena = True
copy_cpu_variant_if_needed(args.cpu_variant)
soc_kwargs = soc_core_argdict(args)
soc_kwargs["l2_size"] = 8 * 1024
soc_kwargs["uart_name"] = "sim"
soc = SimSoC(integrated_main_ram_size=32 * 1024 * 1024,
integrated_main_ram_init=bin,
sim_debug=True,
**soc_kwargs)
if args.separate_arena:
soc.add_config('SOC_SEPARATE_ARENA')
soc.add_ram(
"arena",
origin=0x60000000,
size=256 * 1024,
)
else:
# size-zero .arena region (linker script needs it)
region = SoCRegion(0x60000000, 0, cached=True, linker=True)
soc.bus.add_region("arena", region)
if args.cfu_mport:
#
# add 4 read-only ports with LSBs fixed to 00, 01, 10, and 11.
# and connect them to the CFU
#
newport = []
for i in range(4):
newport.append(soc.arena.mem.get_port())
soc.specials += newport[i]
p_adr_from_cfu = Signal(14)
p_adr = Cat(Constant(i, 2), p_adr_from_cfu)
p_dat_r = Signal(32)
soc.comb += [
p_dat_r.eq(newport[i].dat_r),
newport[i].adr.eq(p_adr),
]
soc.cpu.cfu_params.update(**{f"o_port{i}_addr": p_adr_from_cfu})
soc.cpu.cfu_params.update(**{f"i_port{i}_din": p_dat_r})
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=soc.clk_freq)
sim_config.add_module("serial2console", "serial")
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
builder = Builder(soc, **builder_argdict(args))
# configure_sim_builder(builder, args.sim_rom_bin)
builder.build(build=args.run,
run=args.run,
sim_config=sim_config,
trace=args.sim_trace,
trace_fst=True,
trace_start=int(float(args.sim_trace_start)),
trace_end=int(float(args.sim_trace_end)))
