def __init__(self, **kwargs):
min_rom = 0x9000
if kwargs["integrated_rom_size"] < min_rom:
kwargs["integrated_rom_size"] = min_rom
super().__init__(**kwargs)
if self.args.sim:
return
# SPD EEPROM I2C ---------------------------------------------------------------------------
self.submodules.i2c = I2CMaster(self.platform.request("i2c"))
self.add_csr("i2c")
# ZynqUS+ PS -------------------------------------------------------------------------------
self.submodules.ps = ZynqUSPS()
# Configure PS->PL AXI
# AXI(32) -> AXILite(32) -> WishBone(32) -> SoC Interconnect
axi_ps = self.ps.add_axi_gp_fpd_master(data_width=32)
axi_lite_ps = axi.AXILiteInterface(data_width=32, address_width=40)
self.submodules += axi.AXI2AXILite(axi_ps, axi_lite_ps)
# Use M_AXI_HPM0_FPD base address thaht will fit our whole address space (0x0004_0000_0000)
base_address = None
for base, size in self.ps.PS_MEMORY_MAP['gp_fpd_master'][0]:
if size >= 2**30 - 1:
base_address = base
break
assert base_address is not None
def chunks(lst, n):
for i in range(0, len(lst), n):
yield lst[i:i + n]
addr_str = '_'.join(chunks('{:012x}'.format(base_address), 4))
self.logger.info("Connecting PS AXI master from PS address {}.".format(
colorer('0x' + addr_str)))
wb_ps = wishbone.Interface(
adr_width=40 -
2) # AXILite2Wishbone requires the same address widths
self.submodules += axi.AXILite2Wishbone(axi_lite_ps,
wb_ps,
base_address=base_address)
# silently ignores address bits above 30
self.bus.add_master(name='ps_axi', master=wb_ps)
def __init__(self, **kwargs):
super().__init__(**kwargs)
# ZynqUS+ PS -------------------------------------------------------------------------------
if not self.args.sim:
# Add Zynq US+ PS wrapper
self.submodules.ps = ZynqUSPS()
# Configure PS->PL AXI
# AXI(128) -> AXILite(128) -> AXILite(32) -> WishBone(32) -> SoC Interconnect
axi_ps = self.ps.add_axi_gp_fpd_master()
axi_lite_ps = axi.AXILiteInterface(
data_width=axi_ps.data_width,
address_width=axi_ps.address_width)
self.submodules += axi.AXI2AXILite(axi_ps, axi_lite_ps)
axi_lite_ps_32 = axi.AXILiteInterface(data_width=32,
address_width=40)
self.submodules += axi.AXILiteConverter(axi_lite_ps,
axi_lite_ps_32)
# Use M_AXI_HPM0_FPD base address thaht will fit our whole address space (0x0004_0000_0000)
base_address = None
for base, size in self.ps.PS_MEMORY_MAP['gp_fpd_master'][0]:
if size >= 2**30 - 1:
base_address = base
break
assert base_address is not None
def chunks(lst, n):
for i in range(0, len(lst), n):
yield lst[i:i + n]
addr_str = '_'.join(chunks('{:012x}'.format(base_address), 4))
self.logger.info(
"Connecting PS AXI master from PS address {}.".format(
colorer('0x' + addr_str)))
wb_ps = wishbone.Interface(
adr_width=40 -
2) # AXILite2Wishbone requires the same address widths
self.submodules += axi.AXILite2Wishbone(axi_lite_ps_32,
wb_ps,
base_address=base_address)
# silently ignores address bits above 30
self.bus.add_master(name='ps_axi', master=wb_ps)
def __init__(self,
sys_clk_freq=int(100e6),
with_pwm=False,
with_gpio=False,
gpio_width=32,
with_spi_master=False,
spi_master_data_width=8,
spi_master_clk_freq=8e6,
**kwargs):
platform = Platform(_io)
# UART
if kwargs["with_uart"]:
platform.add_extension([(
"serial",
0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
)])
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"),
rst=platform.request("sys_rst"))
# SoCMini ----------------------------------------------------------------------------------
print(kwargs)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# SPI Master
if with_spi_master:
platform.add_extension([(
"spi_master",
0,
Subsignal("clk", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("mosi", Pins(1)),
Subsignal("miso", Pins(1)),
)])
self.submodules.spi_master = SPIMaster(
pads=platform.request("spi_master"),
data_width=spi_master_data_width,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=spi_master_clk_freq,
)
self.add_csr("spi_master")
# PWM
if with_pwm:
platform.add_extension([("pwm", 0, Pins(1))])
self.submodules.pwm = PWM(platform.request("pwm"))
self.add_csr("pwm")
# GPIO
if with_gpio:
platform.add_extension([("gpio", 0, Pins(gpio_width))])
self.submodules.gpio = GPIOTristate(platform.request("gpio"))
self.add_csr("gpio")
# Wishbone Master
if kwargs["bus"] == "wishbone":
wb_bus = wishbone.Interface()
self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb"))
wb_pads = platform.request("wb")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# AXI-Lite Master
if kwargs["bus"] == "axi":
axi_bus = axi.AXILiteInterface(data_width=32, address_width=32)
wb_bus = wishbone.Interface()
axi2wb = axi.AXILite2Wishbone(axi_bus, wb_bus)
self.submodules += axi2wb
self.bus.add_master(master=wb_bus)
platform.add_extension(axi_bus.get_ios("axi"))
axi_pads = platform.request("axi")
self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave")
# IRQs
for name, loc in sorted(self.irq.locs.items()):
module = getattr(self, name)
platform.add_extension([("irq_" + name, 0, Pins(1))])
irq_pin = platform.request("irq_" + name)
self.comb += irq_pin.eq(module.ev.irq)
def __init__(self,
sys_clk_freq=int(100e6),
with_pwm=False,
with_mmcm=False,
with_gpio=False,
gpio_width=32,
with_spi_master=False,
spi_master_data_width=8,
spi_master_clk_freq=8e6,
**kwargs):
platform = Platform(_io)
# UART
if kwargs["with_uart"]:
platform.add_extension([(
"serial",
0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
)])
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"),
rst=platform.request("sys_rst"))
# SoCMini ----------------------------------------------------------------------------------
print(kwargs)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# MMCM
if with_mmcm:
platform.add_extension([(
"clkgen",
0,
Subsignal("ref", Pins(1)),
Subsignal("out0", Pins(1)),
Subsignal("out1", Pins(1)),
Subsignal("locked", Pins(1)),
)])
self.clock_domains.cd_out0 = ClockDomain(reset_less=True)
self.clock_domains.cd_out1 = ClockDomain(reset_less=True)
self.submodules.mmcm = mmcm = S7MMCM()
mmcm.expose_drp()
self.add_csr("mmcm")
clkgen = platform.request("clkgen")
mmcm.register_clkin(clkgen.ref, 100e6)
mmcm.create_clkout(self.cd_out0, 148.5e6, with_reset=False)
mmcm.create_clkout(self.cd_out1, 742.5e6, with_reset=False)
self.comb += [
clkgen.out0.eq(self.cd_out0.clk),
clkgen.out1.eq(self.cd_out1.clk),
clkgen.locked.eq(mmcm.locked),
]
# SPI Master
if with_spi_master:
platform.add_extension([(
"spi_master",
0,
Subsignal("clk", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("mosi", Pins(1)),
Subsignal("miso", Pins(1)),
)])
self.submodules.spi_master = SPIMaster(
pads=platform.request("spi_master"),
data_width=spi_master_data_width,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=spi_master_clk_freq,
)
self.add_csr("spi_master")
# PWM
if with_pwm:
platform.add_extension([("pwm", 0, Pins(1))])
self.submodules.pwm = PWM(platform.request("pwm"))
self.add_csr("pwm")
# GPIO
if with_gpio:
platform.add_extension([("gpio", 0, Pins(gpio_width))])
self.submodules.gpio = GPIOTristate(platform.request("gpio"))
self.add_csr("gpio")
# Wishbone Master
if kwargs["bus"] in ["wishbone"]:
wb_bus = wishbone.Interface()
self.bus.add_master(master=wb_bus)
platform.add_extension(wb_bus.get_ios("wb"))
wb_pads = platform.request("wb")
self.comb += wb_bus.connect_to_pads(wb_pads, mode="slave")
# AXI-Lite Master
if kwargs["bus"] in ["axi", "axi_lite"]:
axi_bus = axi.AXILiteInterface(data_width=32, address_width=32)
wb_bus = wishbone.Interface()
axi2wb = axi.AXILite2Wishbone(axi_bus, wb_bus)
self.submodules += axi2wb
self.bus.add_master(master=wb_bus)
platform.add_extension(axi_bus.get_ios("axi"))
axi_pads = platform.request("axi")
self.comb += axi_bus.connect_to_pads(axi_pads, mode="slave")
# IRQs
for name, loc in sorted(self.irq.locs.items()):
module = getattr(self, name)
platform.add_extension([("irq_" + name, 0, Pins(1))])
irq_pin = platform.request("irq_" + name)
self.comb += irq_pin.eq(module.ev.irq)