def phy_layout(mode): if mode == "raw": param_layout = frame_timing_layout # not used payload_layout = [("c0", 10), ("c1", 10), ("c2", 11)] return stream.EndpointDescription(payload_layout, param_layout) else: param_layout = frame_timing_layout payload_layout = [("r", 8), ("g", 8), ("b", 8)] return stream.EndpointDescription(payload_layout, param_layout)
def __init__(self, layout, payload_depth, param_depth=None, buffered=False): self.sink = sink = stream.Endpoint(layout) self.source = source = stream.Endpoint(layout) # # # # Parameters. param_layout = sink.description.param_layout payload_layout = sink.description.payload_layout if param_layout == []: param_layout = [("dummy", 1)] if param_depth is None: param_depth = payload_depth # Create the FIFOs. payload_description = stream.EndpointDescription( payload_layout=payload_layout) param_description = stream.EndpointDescription( param_layout=param_layout) param_depth = param_depth + 1 # +1 to allow dequeuing current while enqueuing next. self.submodules.payload_fifo = payload_fifo = stream.SyncFIFO( payload_description, payload_depth, buffered) self.submodules.param_fifo = param_fifo = stream.SyncFIFO( param_description, param_depth, buffered) # Connect Sink to FIFOs. self.comb += [ sink.connect(param_fifo.sink, keep=set([e[0] for e in param_layout])), sink.connect(payload_fifo.sink, keep=set([e[0] for e in payload_layout] + ["last"])), param_fifo.sink.valid.eq(sink.valid & sink.last), payload_fifo.sink.valid.eq(sink.valid & payload_fifo.sink.ready), sink.ready.eq(param_fifo.sink.ready & payload_fifo.sink.ready), ] # Connect FIFOs to Source. self.comb += [ param_fifo.source.connect(source, omit={"last", "ready", "dummy"}), payload_fifo.source.connect(source, omit={"valid", "ready"}), param_fifo.source.ready.eq(source.valid & source.last & source.ready), payload_fifo.source.ready.eq(source.valid & source.ready), ]
def __init__(self, maxlen=65535, dw=256, error_counter_width=32): # Test frame (sink) self.sink = sink = stream.Endpoint( K2MMPacket.packet_user_description(dw=dw)) self.source_tf_status = source_tf_status = stream.Endpoint( stream.EndpointDescription([("err", 1), ("length", log2_int(maxlen + 1))])) # # # beats = Signal(max=maxlen, reset_less=True) data_matched = Signal() self.comb += [ data_matched.eq((sink.data == Replicate(beats, dw // len(beats))) & (sink.valid & sink.ready)), sink.ready.eq(1) ] _frame_err = Signal() # Counter self.sync += [ If( sink.valid & sink.ready, If( sink.last, beats.eq(0), _frame_err.eq(0), source_tf_status.valid.eq(1), source_tf_status.err.eq(_frame_err), source_tf_status.length.eq((beats + 1) * (dw // 8)), ).Else(source_tf_status.valid.eq(0), beats.eq(beats + 1), _frame_err.eq(_frame_err | ~data_matched))).Else( source_tf_status.valid.eq(0)) ]
def __init__(self, data_width=32, user_width=0): self.data_width = data_width self.user_width = user_width payload_layout = [("data", data_width)] param_layout = [] if self.user_width: param_layout += [("user", user_width)] stream.Endpoint.__init__(self, stream.EndpointDescription(payload_layout, param_layout))
def testFrameDescriptor(dw): _payload_layout = [ ("data", dw), ] _param_layout = [ ("length", 16), ] return stream.EndpointDescription(_payload_layout, _param_layout)
def etherbone_packet_user_description(dw): layout = etherbone_packet_header.get_layout() layout = _remove_from_layout(layout, "magic", "portsize", "addrsize", "version") layout += user_description(dw).payload_layout return stream.EndpointDescription(layout)
def etherbone_mmap_description(dw): layout = [ ("we", 1), ("count", 8), ("base_addr", 32), ("be", dw//8), ("addr", 32), ("data", dw) ] return stream.EndpointDescription(layout)
def etherbone_record_description(dw): layout = etherbone_record_header.get_layout() layout += [("data", dw)] return stream.EndpointDescription(layout)
def user_description(dw): layout = [("data", 32), ("length", 32)] return stream.EndpointDescription(layout)
def phy_description(dw): layout = [("data", dw)] return stream.EndpointDescription(layout)
def wrap_description(dw): payload_layout = [ ("data", dw), ] return stream.EndpointDescription(payload_layout)
def getControlInterfaceDescriptor(maxlen=65536): return stream.EndpointDescription([("length", log2_int(maxlen))])
def ulpi_cmd_description(dw, cmddw): payload_layout = [ ("data", dw), ("cmd", cmddw), ] return stream.EndpointDescription(payload_layout)
def __init__(self, platform, pads, refclk, cd="sys", cd_freerun="sys", lanes=4): _dp_layout = stream.EndpointDescription([ ("data", 64 * lanes), # ("keep", (64 * lanes) // 8) ] ) self.platform = platform self.sink_user_tx = stream.Endpoint(_dp_layout) self.source_user_rx = stream.Endpoint(_dp_layout) self.clock_domains.cd_datapath = cd_datapath = ClockDomain() self.init_clk_locked = init_clk_locked = Signal() channel_up = Signal() self.comb += cd_datapath.rst.eq(~channel_up) # CDC self.submodules.cdc_tx = cdc_tx = ClockDomainsRenamer({"write" : cd, "read" : "datapath"})( XPMAsyncStreamFIFO(self.sink_user_tx.description, depth=128, buffered=True, sync_stages=4, reset="source")) self.submodules.cdc_rx = cdc_rx = ClockDomainsRenamer({"write" : "datapath", "read" : cd})( XPMAsyncStreamFIFO(self.source_user_rx.description, depth=128, buffered=True, sync_stages=4)) self.comb += [ self.sink_user_tx.connect(cdc_tx.sink), cdc_rx.source.connect(self.source_user_rx), ] self._reset = CSRStorage(fields=[ CSRField("reset_pb", size=1, offset=0, description="""Write `1` to reset"""), ]) self._status = CSRStatus(fields=[ CSRField("lane_up", size=lanes), CSRField("channel_up", size=1), ]) # Status Register self.specials += MultiReg(channel_up, self._status.fields.channel_up, odomain=cd, n=2) lane_up = Signal(lanes) self.specials += MultiReg(lane_up, self._status.fields.lane_up, odomain=cd, n=2) import util.xilinx_ila for ep in [cdc_tx.source, cdc_rx.sink]: for s in [ep.valid, ep.ready, ep.last]: platform.ila.add_probe(s, cd_datapath.clk, trigger=True) for s in ep.payload.flatten(): platform.ila.add_probe(s, cd_datapath.clk, trigger=False) # clock buffer if isinstance(refclk, Record): self.gt_refclk = Signal() self.specials += Instance( "IBUFDS_GTE4", name="gtref_b", i_I = refclk.p, i_IB = refclk.n, i_CEB = 0b0, o_O = self.gt_refclk) else: self.gt_refclk = refclk self.core_params = dict( i_clk = ClockSignal(cd_freerun), i_reset = self._reset.fields.reset_pb, o_channel_up = channel_up, o_lane_up = lane_up, o_user_clk = ClockSignal(cd="datapath"), i_init_clk_locked = init_clk_locked, # User data TX/RX i_s_axis_tx_tdata = cdc_tx.source.data, i_s_axis_tx_tlast = cdc_tx.source.last, i_s_axis_tx_tvalid = cdc_tx.source.valid, o_s_axis_tx_tready = cdc_tx.source.ready, o_m_axis_rx_tdata = cdc_rx.sink.data, o_m_axis_rx_tlast = cdc_rx.sink.last, o_m_axis_rx_tvalid = cdc_rx.sink.valid, # GTY Pads i_gtyrxn = pads.rx_n, i_gtyrxp = pads.rx_p, o_gtytxn = pads.tx_n, o_gtytxp = pads.tx_p, i_gt_refclk = self.gt_refclk, )
def __init__(self, ddr_wr_port, ddr_rd_port, udp_port): SIZE = 1024 * 1024 SIZE = 1024 self.fifo_full = CSRStatus(reset=0) self.fifo_error = CSRStatus(reset=0) self.fifo_load = CSRStorage( reset=0) # Load the coefficients in memory to the ROI Summer self.fifo_read = CSRStorage(reset=0) self.fifo_size = CSRStorage(32, reset=SIZE) self.dst_ip = CSRStorage(32, reset=convert_ip("192.168.1.114")) self.dst_port = CSRStorage(16, reset=7778) dw = 64 print( f"Write port: A ({ddr_wr_port.address_width})/ D ({ddr_wr_port.data_width})" ) print( f"Read port: A ({ddr_rd_port.address_width})/ D ({ddr_rd_port.data_width})" ) self.submodules.dram_fifo = dram_fifo = LiteDRAMFIFO( data_width=dw, base=0, depth=SIZE, write_port=ddr_wr_port, read_port=ddr_rd_port, with_bypass=True, ) # self.mf = mf = Signal(reset=0) # mf == More Fragments # self.fragment_offset = fragment_offset = Signal(13, reset=0) # self.identification = identification = Signal(16, reset=0) self.submodules.adcs = adcs = ADCStream(1, dw) self.fifo_counter = fifo_counter = Signal(24) self.load_fifo = load_fifo = Signal() # adc --> buffer_fifo self.submodules.buffer_fifo = buffer_fifo = stream.SyncFIFO( stream.EndpointDescription([("data", dw)]), 256, buffered=True) # buffer_fifo --> dram_fifo fifo_size = Signal(32) self.sync += [ fifo_size.eq(self.fifo_size.storage), If(self.fifo_load.re & self.fifo_load.storage, fifo_counter.eq(0), load_fifo.eq(1)), If(load_fifo & adcs.source.valid, self.fifo_full.status.eq(0), self.fifo_error.status.eq(~dram_fifo.dram_fifo.ctrl.writable), fifo_counter.eq(fifo_counter + 1)), If((fifo_counter == fifo_size - 1) & adcs.source.valid, load_fifo.eq(0), self.fifo_full.status.eq(1)), ] self.comb += [ buffer_fifo.sink.data.eq(adcs.source.data), buffer_fifo.sink.valid.eq(adcs.source.valid & load_fifo), buffer_fifo.source.connect(dram_fifo.sink), ] # fifo --> stride converter self.submodules.stride_converter = sc = stream.Converter( dw, udp_port.dw) self.read_from_dram_fifo = read_from_dram_fifo = Signal() self.comb += [dram_fifo.source.connect(sc.sink)] self.receive_count = receive_count = Signal(24) self.sync += [ If(dram_fifo.source.valid & dram_fifo.source.ready, receive_count.eq(receive_count + 1)).Elif( read_from_dram_fifo == 0, receive_count.eq(0)) ] # --> udp fragmenter --> self.submodules.udp_fragmenter = udp_fragmenter = UDPFragmenter( udp_port.dw) self.sync += read_from_dram_fifo.eq(self.fifo_read.storage) self.comb += If( read_from_dram_fifo, # TODO: There is a bug somewhere in the converter, # its source.last somehow gets set, no idea why. That signal is of no real use # for the fragmenter anyways, so we live without it sc.source.connect(udp_fragmenter.sink, omit={'total_size', 'last'})) # TODO: 8 should be adcstream data width // 8 self.comb += udp_fragmenter.sink.length.eq(fifo_size << log2_int(dw // 8)) self.comb += udp_fragmenter.source.connect(udp_port.sink) self.comb += [ # param udp_port.sink.src_port.eq(4321), udp_port.sink.dst_port.eq(self.dst_port.storage), udp_port.sink.ip_address.eq(self.dst_ip.storage), # udp_port.sink.ip_address.eq(convert_ip("192.168.88.101")), # payload udp_port.sink.error.eq(0) ] # debug self.first_sample, self.last_sample = Signal(16), Signal(16) self.sync += [ If(fifo_counter == 1, self.first_sample.eq(adcs.source.data[:16])), If(fifo_counter == SIZE - 2, self.last_sample.eq(adcs.source.data[:16])), ]
def video_out_layout(dw): param_layout = frame_timing_layout payload_layout = [("data", dw)] return stream.EndpointDescription(payload_layout, param_layout)