def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
platform = de0nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE0-Nano",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16160(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self,
sys_clk_freq=int(50e6),
sdram_rate="1:1",
with_led_chaser=True,
**kwargs):
platform = de0nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE0-Nano",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16160(sys_clk_freq, sdram_rate),
l2_cache_size=kwargs.get("l2_size", 8192))
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
platform = de0nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16160(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads=Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = de0nano.Platform()
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = IS42S16160(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
platform = de0nano.Platform()
platform.toolchain.additional_qsf_commands = [
'set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"',
'set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"',
]
platform.toolchain.additional_sdc_commands = [
'create_clock -name eth_rx_clk -period 20 [get_ports eth_clocks_ref_clk]',
'create_clock -name eth_rx_clk_virt -period 20',
'derive_clock_uncertainty',
'set CLKAs_max 0.0',
'set CLKAs_min 0.0',
'set CLKAd_max 1.13',
'set CLKAd_min 0.87',
'set tCOa_max 16',
'set tCOa_min 1',
'set BDa_max 1.13',
'set BDa_min 0.87',
'set_input_delay -clock eth_rx_clk_virt -max [expr $CLKAs_max + $tCOa_max + $BDa_max - $CLKAd_min] [get_ports {eth_rx_data[*] eth_crs_dv}]',
'set_input_delay -clock eth_rx_clk_virt -min [expr $CLKAs_min + $tCOa_min + $BDa_min - $CLKAd_max] [get_ports {eth_rx_data[*] eth_crs_dv}]',
]
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
platform,
sys_clk_freq,
ident="LiteX SoC on DE0-Nano",
ident_version=True,
cpu_type="vexriscv_smp",
cpu_variant="linux",
max_sdram_size=0x40000000, # Limit mapped SDRAM to 1GB.
**kwargs)
# Add linker region for OpenSBI
self.add_memory_region("opensbi",
self.mem_map["main_ram"] + 0x00f00000,
0x80000,
type="cached+linker")
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=IS42S16160(sys_clk_freq, sdram_rate),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# UART -------------------------------------------------------------------------------------
_uart_jp_ios = [("uart", 0,
Subsignal("tx", Pins("JP1:34"),
IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("JP1:32"),
IOStandard("3.3-V LVTTL")))]
self.platform.add_extension(_uart_jp_ios)
self.add_uart(name="uart", baudrate=921600, fifo_depth=1024)
# Leds -------------------------------------------------------------------------------------
led_pads = platform.request_all("user_led")
self.submodules.leds = GPIOOut(led_pads)
self.add_constant("LEDS_NGPIO", len(led_pads))
# Keys -------------------------------------------------------------------------------------
switches_pads = self.platform.request_all("key")
self.submodules.switches = GPIOIn(pads=switches_pads, with_irq=True)
self.irq.add("switches", use_loc_if_exists=True)
self.add_constant("SWITCHES_NGPIO", len(switches_pads))
# RMII Ethernet ----------------------------------------------------------------------------
_ethernet_jp_ios = [
(
"eth_clocks",
0,
Subsignal("ref_clk", Pins("JP2:34")),
IOStandard("3.3-V LVTTL"),
),
(
"eth",
0,
#Subsignal("rst_n", Pins("")),
Subsignal("rx_data", Pins("JP2:36 JP2:35")),
Subsignal("crs_dv", Pins("JP2:33")),
Subsignal("tx_en", Pins("JP2:38")),
Subsignal("tx_data", Pins("JP2:37 JP2:40")),
Subsignal("mdc", Pins("JP2:31")),
Subsignal("mdio", Pins("JP2:32")),
#Subsignal("rx_er", Pins("")),
#Subsignal("int_n", Pins("")),
IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_ethernet_jp_ios)
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
refclk_cd=None,
)
self.add_ethernet(phy=self.ethphy, nrxslots=4, ntxslots=2)
# SD Card ----------------------------------------------------------------------------------
_sdcard_jp_ios = [
(
"sdcard",
0,
Subsignal("data", Pins("JP2:14 JP2:24 JP2:22 JP2:20"),
Misc("WEAK_PULL_UP_RESISTOR ON")),
Subsignal("cmd", Pins("JP2:16"),
Misc("WEAK_PULL_UP_RESISTOR ON")),
Subsignal("clk", Pins("JP2:18")),
Subsignal("cd", Pins("JP2:26")),
Misc("FAST_OUTPUT_REGISTER ON"),
IOStandard("3.3-V LVTTL"),
),
]
#_sdcard_jp_ios = [
# ("spisdcard", 0,
# Subsignal("miso", Pins("JP2:14"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Subsignal("mosi", Pins("JP2:16"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Subsignal("clk", Pins("JP2:18")),
# Subsignal("cs_n", Pins("JP2:20"), Misc("WEAK_PULL_UP_RESISTOR ON")),
# Misc("FAST_OUTPUT_REGISTER ON"),
# IOStandard("3.3-V LVTTL"),
# ),
#]
self.platform.add_extension(_sdcard_jp_ios)
self.add_sdcard()
#self.add_spi_sdcard()
# EPCS ------------------------------------------------------------------------------------
_spi_flash_ios = [
("spiflash", 0, Subsignal("miso", Pins("H2")),
Subsignal("clk", Pins("H1")), Subsignal("cs_n", Pins("D2")),
Subsignal("mosi", Pins("C1")), IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_spi_flash_ios)
self.add_spi_flash(mode="1x", dummy_cycles=8)
# I2C ADXL345 -----------------------------------------------------------------------------
_i2c_ios = [
("i2c_onboard", 0, Subsignal("scl", Pins("F2")),
Subsignal("sda", Pins("F1")), IOStandard("3.3-V LVTTL")),
]
self.platform.add_extension(_i2c_ios)
self.submodules.i2c0 = I2CMaster(
self.platform.request("i2c_onboard", 0))
adxl_pads = self.platform.request("acc")
self.comb += adxl_pads.cs_n.eq(1)
# ADC -------------------------------------------------------------------------------------
_spi_ios = [("adc128s", 0, Subsignal("cs_n", Pins("A10")),
Subsignal("mosi",
Pins("B10")), Subsignal("clk", Pins("B14")),
Subsignal("miso", Pins("A9")), IOStandard("3.3-V LVTTL"))]
self.platform.add_extension(_spi_ios)
spi_pads = self.platform.request("adc128s")
self.submodules.spi = SPIMaster(spi_pads, 8, self.clk_freq, 1e6)
self.add_csr("spi")
# interrupts ------------------------------------------------------------------------------
#_interrupts_jp_ios = [
# ("interrupt", 0, Pins("JP2:1"), IOStandard("3.3-V LVTTL")),
# ("interrupt", 1, Pins("JP2:26"), IOStandard("3.3-V LVTTL")),
#]
#self.platform.add_extension(_interrupts_jp_ios)
#interrupts_pads = self.platform.request_all("interrupt")
interrupts_pads = adxl_pads.int
self.submodules.interrupts = GPIOIn(interrupts_pads, with_irq=True)
self.irq.add("interrupts", use_loc_if_exists=True)
self.add_constant("INTERRUPTS_NGPIO", len(interrupts_pads))
