def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", spiflash=False, **kwargs): platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain) if spiflash: self.mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}} # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on ULX3S", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, device="LFE5U-45F", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs): platform = ulx3s.Platform(device=device, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy=self.sdrphy, module=getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1"), origin=self.mem_map["main_ram"], size=kwargs.get("max_sdram_size", 0x40000000), l2_cache_size=kwargs.get("l2_size", 8192), l2_cache_min_data_width=kwargs.get( "min_l2_data_width", 128), l2_cache_reverse=True)
def __init__(self, device="LFE5U-45F", toolchain="diamond", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs): platform = ulx3s.Platform(device=device, toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, integrated_rom_size=0x8000, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) sdram_module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, with_spi_flash=False, **kwargs): platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on ULX3S", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" with_video_pll = with_video_terminal or with_video_framebuffer self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll, with_video_pll, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate), size = 0x40000000, l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_reverse = False ) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") # SPI Flash -------------------------------------------------------------------------------- if with_spi_flash: from litespi.modules import IS25LP128 from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="4x", module=IS25LP128(Codes.READ_1_1_4)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)
def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", with_video_terminal=False, with_video_framebuffer=False, spiflash=False, **kwargs): platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain) if spiflash: self.mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}} # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on ULX3S", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" with_video_pll = with_video_terminal or with_video_framebuffer self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll, with_video_pll, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate), size = 0x40000000, l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_reverse = False ) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi") if with_video_terminal: self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") if with_video_framebuffer: self.add_video_framebuffer(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") self.comb += platform.request("ext0p").eq(self.video_framebuffer.underflow) # FIXME: Remove, used to debug SDRAM underflows. # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq)