def matchesCommand(Wrd0):
res = []
for Comm in ValidCommands:
if startsTheSame(Wrd0, Comm):
res.append(Comm)
if len(res) == 1:
return res[0]
if len(res) > 1:
logs.log_warning('ambigious command %s matches %s' % (Wrd0, res))
elif len(res) == 0:
logs.log_info('valid cmds: %s' % ValidCommands)
return False
def createXml(Module,Db):
print('db %s'%Db.keys())
Chip = Db['chip']
Items = Db['regs']
Range = Chip.Addr+4
Fout = open('%s.xml'%Module,'w')
Str = string.replace(HEADER,'NAME',Module)
Str = string.replace(Str,'LIBRARY','AutoTalksLib')
Str = string.replace(Str,'BASEADDR','0')
Str = string.replace(Str,'RANGE','%x'%Range)
Fout.write(Str)
for Item in Items:
# print(Item.Kind,Item.Params)
if Item.Kind=='ram':
Acc = 'ram'
Amount = Item.Params['depth']
else:
Acc = Item.Params['access']
Amount = 0
Wid = Item.Params['width']
Reg = Item.Params['names'][0]
if 'desc' not in Item.Params:
Desc = 'DESC NOT GIVEN'
logs.log_warning('description of %s not given'%Reg)
else:
Desc = Item.Params['desc']
if 'reset' not in Item.Params:
Reset = 0
else:
Reset = Item.Params['reset']
Addr = Item.Addr
# Fout.write('item %s %x %s\n'%(Item.Kind,Item.Addr,Item.Params))
if Wid<=32:
writeItem(Fout,Acc,Addr,Wid,Reset,Desc,Reg,Amount)
else:
Acc0 = Acc
Acc = string.replace(Acc,'_pulse','')
Run = 0
while Wid>32:
writeItem(Fout,Acc,Addr,32,Reset,Desc,Reg+'_%d'%Run,Amount)
Addr += 4
Run += 1
Wid -= 32
writeItem(Fout,Acc,Addr,Wid,Reset,Desc,Reg+'_%d'%Run,Amount)
Fout.write(TRAILER)
Fout.close()
def dealVsignals(dbscan):
for Module in dbscan.Modules:
Mod = dbscan.Modules[Module]
ind = 0
if Mod.vsignals == []: return
Vsignals = Mod.vsignals[0]
while ind < len(Vsignals):
Item = Vsignals[ind]
if Item[0] == 'component':
COMPONENTS[Item[1]] = []
for Port in Item[3]:
COMPONENTS[Item[1]].append(Port[1])
Vsignals.pop(ind)
elif Item[0] == 'type':
Name = Item[1]
print('ENUMS', Item[2])
Mod.enums[Name] = ('singles', Item[2])
Vsignals.pop(ind)
elif Item[0] == 'doublearray':
AA = getWid(Item[2])
BB = getWid(Item[3])
Types[Item[1]] = ('double', BB, AA)
Vsignals.pop(ind)
elif Item[0] == 'constant':
Mod.localparams[Item[1]] = Item[2]
Vsignals.pop(ind)
elif Item[0].lower() == 'signal':
Vsignals.pop(ind)
for Sig in Item[1]:
if Item[2] == 'std_logic':
Mod.add_sig(Sig, 'logic', 0)
elif Item[2] == 'std_logic_vector':
Wid = getWid(Item[3])
Mod.add_sig(Sig, 'logic', Wid)
elif Item[2] in ['integer', 'unsigned', 'natural']:
Mod.add_sig(Sig, 'logic', (31, 0))
elif Item[2] in Types:
Def = Types[Item[2]]
if Def[0] == 'double':
Mod.add_sig(Sig, 'logic', ('packed', AA, BB))
else:
Mod.add_sig(Sig, Item[2], 0)
elif Item[0] == 'assign':
Vsignals.pop(ind)
logs.log_warning('INIT ASSIGN not used %s' % str(Item))
else:
logs.log_error('VSIGNALS %s' % str(Item))
ind += 1
def load_init_file():
found = False
homepath = '%s/.zdrawrc' % (os.path.expanduser('~'))
herepath = '%s/.zdrawrc' % (os.path.abspath('.'))
logs.log_info('home %s' % homepath)
logs.log_info('here %s' % herepath)
if os.path.exists(homepath):
read_init_file(homepath)
logs.log_info('home dir .zdrawrc loaded')
found = True
if os.path.exists(herepath):
read_init_file(herepath)
logs.log_info('pwd dir .zdrawrc loaded')
found = True
if not found:
logs.log_warning('no .zdrawrc loaded')
def dffx1(Obj, Mod):
D = trans(Obj.conns['D'])
CK = trans(Obj.conns['CK'])
Q, QN = getQandQN(Obj, Mod)
Cond = ('edge', 'posedge', CK)
if (Q == '') and (QN == ''):
logs.log_warning('no Q, QN in dffx1 %s' % Obj.Name)
return True
if (QN == ''):
Mod.alwayses.append((Cond, ('<=', Q, D), 'always'))
elif (Q == ''):
Mod.alwayses.append((Cond, ('<=', QN, ('!', D)), 'always'))
else:
Mod.alwayses.append((Cond, ('<=', Q, D), 'always'))
Mod.hard_assigns.append((QN, ('!', Q), '', ''))
return True
def workIncludes(self):
Dones = True
while Dones:
Dones = False
Seq = []
for ind, Linex in enumerate(self.Sequence):
try:
Line, x = Linex
except:
Line = Linex
x = '???'
wrds = Line.split()
if (len(wrds) == 0) or (wrds[0][0] in '#/'):
pass
elif (wrds[0] == 'include'):
Fname = wrds[1]
Fname = os.path.expanduser(Fname)
Fname = os.path.expandvars(Fname)
Fname = os.path.abspath(Fname)
Found = False
if os.path.exists(Fname):
Lines = open(Fname).readlines()
for x, Line in enumerate(Lines):
Seq.append((Line, 1000 + x))
Found = True
Dones = True
for Path in self.searchPath:
if (not Found) and os.path.exists('%s/%s' %
(Path, Fname)):
Lines = open('%s/%s' % (Path, Fname)).readlines()
for xx, LL in enumerate(Lines):
Seq.append((LL, xx))
Found = True
Dones = True
if not Found:
logs.log_warning('include file "%s" no found in %s' %
(Fname, self.searchPath))
Dones = False
else:
Seq.append((Line, x))
self.Sequence = Seq
def readQueue(self, arlen, ii, burst, arsize, addr, rid, rlast):
if (arsize > 4): arsize = 4
Incr = 1 << arsize
Mask = ~((1 << arsize) - 1)
Mask2 = ((1 << arsize) - 1)
if burst == 0:
Addr = addr
elif burst == 1:
Addr = ii * Incr + addr
elif burst == 2:
Len = (arlen + 1) * (1 << arsize)
Maskw = ~(Len - 1)
Maskw2 = (Len - 1)
Base = addr & Maskw
Addr = ii * Incr + addr
Pos = Addr & Maskw2
Addr = Base + Pos
else:
logs.log_error('BURST %s' % burst)
Addr = addr
Addr1 = Addr & Mask
if Addr1 != Addr:
logs.log_warning(
'axiSlave read address is not aligned size=%d addrin=%08x' %
(arsize, Addr))
rdata = ''
takenram = 0
for jj in range(Incr):
Add = Addr1 + jj
if Add in self.Ram:
AA = '%02x' % (self.Ram[Add])
takenram += 1
else:
AA = '%02x' % (self.bytex)
self.bytex = (self.bytex + 1) & 0xff
rdata = AA + rdata
self.rqueue.append((rlast, rid, rdata))
logs.log_info(
'axiSlave taken from ram %d bytes rdata=%s addr=%08x rid=%x' %
(takenram, rdata, Addr, rid))
def readQueue(self,ii,addr):
Addr = addr
Addr1 = Addr & Mask
if Addr1!=Addr:
logs.log_warning('axiSlave %s%s read address is not aligned addrin=%08x'%(self.Prefix,self.Suffix,Addr))
rdata = ''
takenram = 0
for ii in range(16):
Add = Addr1 + ii
if Add in self.Ram:
AA = '%02x'%(self.Ram[Add])
takenram += 1
# logs.log_info('axiSlave %s%s addr in ram %x '%(self.Prefix,self.Suffix,Add))
else:
# AA = '%02x'%(0xff)
AA = '%02x'%(self.bytex)
self.bytex += 1
# logs.log_info('axiSlave %s%s addr not in ram %x '%(self.Prefix,self.Suffix,Add))
rdata = AA + rdata
self.rqueue.append(rdata)
logs.log_info('axiSlave %s%s taken from ram %d bytes rdata=%s addr=%08x'%(self.Prefix,self.Suffix,takenram,rdata,Addr))
def read_init_file(Fname):
File = open(Fname)
while 1:
line = File.readline()
if (len(line) == 0):
return
line = line.replace('=', ' = ')
wrds = line.split()
if (len(wrds) > 0) and (wrds[0] == 'load'):
Fname = figure_out_the_file(wrds[0])
if not Fname:
logs.log_error('file "%s" cant be read' % Fname)
else:
dbase.load_dbase_file(Fname)
elif (len(wrds) >= 2) and (wrds[0] == 'import'):
import_command(wrds[1])
elif (len(wrds) >= 2) and (wrds[0] == 'pics_lib'):
Was = dbase.get_context('pics_lib')
line2 = line.replace(',', ' ')
wrds2 = line2.split()
for wrd in wrds2[1:]:
Was.append(wrd)
dbase.set_context('pics_lib', Was)
elif (len(wrds) == 2):
Param = wrds[0]
Value = wrds[1]
# logs.log_info('read_init_file set context "%s" "%s"'%(Param,Value))
if (',') in Value:
W1 = Value.split(',')
ll = []
for X in W1:
ll.append(makenum(X))
dbase.set_context(Param, ll)
elif (Value[0] in '0123456789'):
dbase.set_context(Param, makenum(Value))
else:
dbase.set_context(Param, Value)
elif (len(wrds) > 0):
logs.log_warning('read_init_file got "%s" . not valid.' %
(' '.join(wrds)))
def travel(Hld,Net,Sofar):
# logs.log_info('%s %s %s'%(Hld.Name,Net,Sofar))
if len(Sofar)>1:
Head = Sofar[0]
if Head in Sofar[1:]:
report('LOOP',Hld.Name,Net,Sofar)
return
if (Net in Hld.TERMS)and(len(Sofar)>1):
report('TOTERM',Hld.Name,Net,Sofar)
return
if Net in Hld.ARCSFW:
Fws = Hld.ARCSFW[Net]
print('FWS',Net,Fws)
for Fw in Fws:
travel(Hld,Fw,[('fw',Hld.Name,Fw)]+Sofar)
if Net in Hld.OUTPUTS:
if Hld.Name in CALLED:
Fathers = CALLED[Hld.Name]
for (Father,Son) in Fathers:
Up = HLDS[Father]
for (S0,P0,Sig) in Up.CONNS:
if (S0 == Son)and(P0==Net):
travel(Up,Sig,[('up',Father,Sig)]+Sofar)
else:
report('TOOUT',Hld.Name,Net,Sofar)
# logs.log_info('TOOUT %s.%s %s\n\n\n'%(Hld.Name,Net,Sofar))
for Inst,Pin,Sig in Hld.CONNS:
if Sig==Net:
for Inst2,Type in Hld.SONS:
if Inst2==Inst:
if Type not in HLDS:
logs.log_warning('%s is not read'%Type)
else:
Son = HLDS[Type]
if Pin in Son.INPUTS:
travel(Son,Pin,[('down',Son.Name,Pin,Hld.Name,Sig)]+Sofar)
def uniquifyFields():
Takens = {}
for Reg in Db['regs']:
Name = Reg.Name
if Name in Db['fields']:
List = Db['fields'][Name]
for Field in List:
Fname = Field.Name
if Fname == 'gap':
pass
elif Fname in Takens:
Takens[Fname].append((Field, Reg))
else:
Takens[Fname] = [(Field, Reg)]
for Fname in Takens:
List = Takens[Fname]
if len(List) > 1:
logs.log_info('duplicate fields %s. uniquifying' % Fname)
for Field, Reg in List:
if 'suffix' in Reg.Params:
Suff = Reg.Params['suffix']
Newname = Fname + Suff
elif 'prefix' in Reg.Params:
Pref = Reg.Params['prefix']
Newname = Pref + Fname
else:
Newname = Reg.Name + '_' + Fname
Field.Name = Newname
Field.Params['names'][0] = Newname
elif (len(List) == 1):
Field, Reg = List[0]
if 'suffix' in Reg.Params:
logs.log_warning(
'no need for suffix in reg=%s field=%s - it is unique' %
(Reg.Name, Field.Name))
if 'prefix' in Reg.Params:
logs.log_warning(
'no need for prefix in reg=%s field=%s - it is unique' %
(Reg.Name, Field.Name))
def gatherFields():
Active = False
Obj = False
Db['fields'] = {}
Db['regs'] = []
for Reg in Db['items']:
if Reg.Kind == 'reg':
Active = Reg.Params['names'][0]
Obj = Reg
Reg.Name = Active
Db['regs'].append(Reg)
if ('access' in Reg.Params) and (Reg.Params['access']
== 'external'):
EXTERNAL_REGS.append(Reg.Name)
elif Reg.Kind == 'field':
if Active:
if ('access'
not in Reg.Params) or (Reg.Params['access'] != 'gap'):
Reg.Params['access'] = Obj.Params['access']
Nreg = Obj.Params['names'][0]
if Nreg not in FIELDED_REGS: FIELDED_REGS.append(Nreg)
if Active not in Db['fields']:
Db['fields'][Active] = [Reg]
else:
Db['fields'][Active].append(Reg)
Reg.Name = Reg.Params['names'][0]
Obj.incs.append(Reg.Name)
else:
logs.log_error('#%d: no reg for field %s' %
(Reg.Lnum, Reg.Params))
else:
Db['regs'].append(Reg)
Active = False
for Reg in Db['regs']:
if len(Reg.incs) == 1:
logs.log_warning(
'#%d: REG "%s" has just one field "%s". this is not needed.' %
(Reg.Lnum, Reg.Name, Reg.incs[0]))
def dffrx1(Obj, Mod):
D = trans(Obj.conns['D'])
CK = trans(Obj.conns['CK'])
RN = trans(Obj.conns['RN'])
Cond = ('list', ('edge', 'posedge', CK), ('edge', 'negedge', RN))
Q, QN = getQandQN(Obj, Mod)
if (Q == '') and (QN == ''):
logs.log_warning('no Q, QN in dffrx1 %s' % Obj.Name)
logs.log_info('%s %s' % ('Q' in Obj.conns, 'QN' in Obj.conns))
return False
if (QN == ''):
Mod.alwayses.append((Cond, ('ifelse', ('!', RN), ('<=', Q, 0),
('<=', Q, D)), 'always'))
elif (Q == ''):
Mod.alwayses.append((Cond, ('ifelse', ('!', RN), ('<=', QN, 1),
('<=', QN, ('!', D))), 'always'))
else:
Mod.alwayses.append((Cond, ('ifelse', ('!', RN), ('<=', Q, 0),
('<=', Q, D)), 'always'))
Mod.hard_assigns.append((QN, ('!', Q), '', ''))
return True
def loadable_pictures(self):
Dirs = self.get_context('pics_lib')
Res = []
if type(Dirs) is list:
for Dir in Dirs:
if os.path.exists(Dir):
LL = os.listdir(Dir)
for Fname in LL:
if '.zpic' in Fname:
Cell = Fname[:-5]
if Cell not in self.pictures:
Res.append(Cell)
elif type(Dirs) is str:
if not os.path.exists(Dirs):
logs.log_warning('no pics directory "%s"' % Dirs)
return []
LL = os.listdir(Dirs)
for Fname in LL:
if '.zpic' in Fname:
Cell = Fname[:-5]
if Cell not in self.pictures:
Res.append(Cell)
return Res
def executeCommands():
global interactiveWait, Queue
while Queue != []:
Cmd = Queue.pop(0)
if '#' in Cmd: Cmd = Cmd[:Cmd.index('#')]
wrds = string.split(Cmd)
if len(wrds) == 0:
pass
elif (wrds[0] == '.'):
runcycle()
elif (len(wrds) == 2) and (wrds[0] == 'run'):
for ii in range(int(wrds[1])):
runcycle()
elif (wrds[0] == 'pause'):
logs.log_info('pause on %s' % str(wrds))
return
elif (wrds[0] == 'assert'):
logs.log_info('assert on %s' % str(wrds))
return
elif (wrds[0] == 'till'):
if len(wrds) == 1:
logs.log_error(
'till needs param running|break and optional max run count'
)
else:
What = wrds[1]
if len(wrds) > 2:
Safe = int(wrds[2])
else:
Safe = 1000
if What[0] == 'r':
while (Safe > 0) and (not weAreRunning()):
runcycle()
Safe -= 1
elif What[0] == 'b':
while (Safe > 0) and (not weAreInBreak()):
runcycle()
Safe -= 1
else:
logs.log_error(
'till command accepts "running" "break" parameters, not "%s"'
% (What))
elif (wrds[0] == 'force'):
for ii in range(1, len(wrds) - 1, 2):
Val = wrds[ii + 1]
try:
X = eval(Val)
except:
X = 0
logs.log_error('forcing %s to "%s" failed.' %
(wrds[ii], Val))
Vals = '%x' % X
veri.force(wrds[ii], Vals)
if (wrds[ii] == 'triggers') and (wrds[ii + 1] != '0'):
if apb.queue0 != []:
logs.log_warning(
'triggers toggled while APB queue is not empty. check that all program is loaded by now (len=%d)'
% (len(apb.queue0)))
elif (wrds[0] == 'peek'):
for ii in range(1, len(wrds)):
Val = veri.peek(wrds[ii])
Str = '%s=0x%x' % (wrds[ii], int(Val, 16))
logs.log_info('%s' % Str)
elif (wrds[0] == 'width'):
for ii in range(1, len(wrds)):
Val = veri.width(wrds[ii])
Str = '%s=%d' % (wrds[ii], int(Val))
logs.log_info('%s' % Str)
elif (wrds[0] == 'include'):
try:
File = open(wrds[1])
print 'file %s opened ' % wrds[1]
lines = File.readlines()
print 'len lines %s' % len(lines)
Queue = lines + Queue
print 'len queue lines %s' % len(Queue)
executeCommands()
print 'after'
except:
# traceback.print_last()
# traceback.print_stack()
logs.log_error('failed to include "%s" file' % (wrds[1]))
elif (wrds[0] == 'define'):
Locals[wrds[1]] = eval(wrds[2], Locals)
elif (wrds[0] == 'cpuf'):
Addr = eval(wrds[1], Locals)
Data = eval(wrds[2], Locals)
veri.cpu_ram_f(str(Addr), str(Data))
elif (wrds[0] == 'cpup'):
Addr = eval(wrds[1], Locals)
Data = veri.cpu_ram_p(str(Addr))
print('cpudata %s' % Data)
elif wrds[0] in ['loadCpu', 'load_cpu']:
if len(wrds) > 1:
loadCpu(wrds[1])
else:
logs.log_error('give application filename to loadCpu')
elif wrds[0] in ['quit', 'exit']:
veri.finish()
sys.exit()
elif wrds[0] in ['axi_peek']:
if len(wrds) == 2:
Many = 16
Addr = eval(wrds[1], Locals)
elif len(wrds) == 3:
Many = eval(wrds[2], Locals)
Addr = eval(wrds[1], Locals)
else:
logs.log_error('axi_peek <Start> <Count>')
Addr = 0
Many = 0
guard = 0
Str = '%06x : ' % Addr
for Run in range(Addr, Addr + Many):
if guard == 16:
logs.log_info(Str)
Str = '%06x : ' % Run
guard = 0
if Run in slave.Ram:
Val = hex(slave.Ram[Run] & 0xff)[2:]
if Val[-1] == 'L': Val = Val[:-1]
if len(Val) < 2: Val = ' ' + Val
else:
Val = ' _'
Str += ' ' + Val
guard += 1
logs.log_info(Str)
elif wrds[0] in ['axi_force']:
if len(wrds) < 2:
logs.log_error('axi_force <Start> HexValues ....')
else:
Addr = eval(wrds[1], Locals)
for wrd in wrds[2:]:
if (len(wrd) >= 2) and (wrd[:2] == '0x'):
wrd = wrd[2:]
while len(wrd) > 0:
try:
Byte = int(wrd[-2:], 16)
except:
logs.log_error('axi_force found "%s" non-hexable' %
(wrd[-2:]))
Byte = 0
wrd = wrd[:-2]
slave.Ram[Addr] = Byte
Addr += 1
elif wrds[0] in ['axi_flood']:
if len(wrds) == 4:
Val = eval(wrds[3], Locals)
else:
Val = 0
if len(wrds) < 3:
logs.log_error('axi_flood <Start> <End> [flood Val]')
else:
Start = eval(wrds[1], Locals)
End = eval(wrds[2], Locals)
for II in range(Start, End + 1):
slave.Ram[II] = Val & 0xff
elif wrds[0] in ['dma_ram']:
Low = eval(wrds[1], Locals)
High = eval(wrds[2], Locals)
for Addr in range(Low, High + 1):
Val = veri.dma_ram(str(Addr))
if Val == (72 * '0'):
res = '@%x: 0 ' % (Addr)
else:
res = '%d @%x: %s ' % (len(Val), Addr, Val)
logs.log_info('%s' % res)
elif wrds[0] in ['ram_peek']:
Low = eval(wrds[1], Locals)
High = eval(wrds[2], Locals)
res = '@%x: ' % (Low * 2)
many = 0
for Addr in range(Low, High + 1):
Val = veri.cpu_ram_p(str(Addr))
res += ' %s' % Val
many += 1
if many == 8:
logs.log_info('%s' % res)
res = '@%x: ' % (2 * (Addr + 1))
many = 0
if many > 0:
logs.log_info('%s' % res)
elif '.' in wrds[0]:
www = string.split(wrds[0], '.')
if www[0] in imported:
exec(string.join(wrds, ' '), locals(), globals())
else:
print 'failed to do \"%s\"' % Cmd
else:
try:
exec(string.join(wrds, ' '), locals(), globals())
print 'exec %s' % str(wrds)
except:
print 'failed to do \"%s\"' % Cmd
def readFile(File):
Lines = createLines(File)
Lines = treatTemplates(Lines)
for Lnum, wrds in Lines:
if (wrds[0] == 'end'):
generate()
return
elif (wrds[0] == 'chip'):
Db['chip'] = itemClass(Lnum, wrds)
else:
Split = False
if wrds[0] == 'array':
Params = getParams(Lnum, wrds[1:])
if ('pulse' in Params['access']) or (Params['width'] > 32):
Split = True
Base = Params['names'][0]
Prepare = 'reg %sNNN width=%s access=%s desc=%s' % (
Params['names'][0], Params['width'], Params['access'],
Params['desc'])
if 'fields' in Params:
Prepare += ' fields=external'
Splitted = [Base, Params['depth']]
Members = []
Members_pulse = []
for II in range(Params['depth']):
Prep = Prepare.replace('NNN', str(II))
wrds = Prep.split()
Item = itemClass(Lnum, wrds)
Db['items'].append(Item)
Kind = Item.Kind
Item.Name = Item.Params['names'][0]
Members.append('%s' % Item.Name)
Members_pulse.append('%s_pulse' % Item.Name)
Splitted.append(Item.Name)
if len(Item.Params['names']) > 0:
Name = Item.Params['names'][0]
Item.Name = Name
checkPair(Item, Kind, Name)
else:
Item.Name = 'none'
Db['splitted'].append(Splitted)
if outAccess(Params['access']):
LINES[0].append(
' ,output [%s-1:0] [%s-1:0] %s' %
(Params['depth'], Params['width'], Base))
Members.reverse()
LINES['split2'].append('assign %s = { %s };' %
(Base, ','.join(Members)))
else:
LINES[0].append(
' ,input [%s-1:0] [%s-1:0] %s' %
(Params['depth'], Params['width'], Base))
LINES['split2'].append('assign { %s } = %s;' %
(','.join(Members), Base))
if ('pulse' in Params['access']):
LINES[0].append(' ,output [%s-1:0] %s_pulse' %
(Params['depth'], Base))
Members_pulse.reverse()
LINES['split2'].append('assign %s_pulse = { %s };' %
(Base, ','.join(Members_pulse)))
if (not Split):
Item = itemClass(Lnum, wrds)
Db['items'].append(Item)
Kind = Item.Kind
if len(Item.Params['names']) > 0:
Name = Item.Params['names'][0]
Item.Name = Name
checkPair(Item, Kind, Name)
else:
Item.Name = 'none'
logs.log_warning('You should have "end" line as last line.')
generate()
def printScreen():
logs.log_warning('print screen - not yet.')
def computeWidthFromFields():
Db['splits'] = {}
Db['splitsw'] = {}
for Reg in Db['regs']:
Name = Reg.Name
if (Name != 'none') and (Reg.Kind in ['reg', 'array', 'ram']):
Name = Reg.Name
OrigWid = getPrm(Reg, 'width', 0)
OrigReset = getPrm(Reg, 'reset', 0)
Ptr = 0
Wid = 0
Map = []
BuildReset = 0
if Name in Db['fields']:
List = Db['fields'][Name]
for Obj in List:
Name = getPrm(Obj, 'names', ['err'])[0]
Obj.Name = Name
Add0 = getPrm(Obj, 'width', 0)
Add = getPrm(Obj, 'width', 0)
if Add == 0:
logs.log_error('#%d: reg %s field %s has no width' %
(Reg.Lnum, Name, Obj.Name))
Align = getPrm(Obj, 'align', 0)
if (Align > 0):
if (Align <= Add):
logs.log_error(
'#%d: field %s of reg %s has bith width and align. align is smaller.'
% (Reg.Lnum, Obj.Name, Name))
else:
Add = Align
Db['splits'][Reg.Name] = Reg
Obj.Params['position'] = (Wid + Add0 - 1, Wid)
while (len(Map) < (Wid + Add0)):
Map.append('0')
if (Name == 'gap'):
for X in range(Wid + Add0 - 1, Wid - 1, -1):
Map[X] = '0'
Db['splits'][Reg.Name] = Reg
else:
for X in range(Wid + Add0 - 1, Wid - 1, -1):
Map[X] = '1'
if 'reset' in Obj.Params:
Freset = Obj.Params['reset']
Bin = len(bin(Freset)) - 2
if Add0 < Bin:
logs.log_error(
'#%d: reset value 0x%x of field %s of reg %s is wider than bits allocated to it = %d'
% (Reg.Lnum, Freset, Name, Reg.Name, Add0))
Freset = Freset & ((1 << Add) - 1)
BuildReset |= (Freset << Wid)
Wid += Add
if OrigWid == 0:
Reg.Params['width'] = Wid
elif (OrigWid < Wid):
logs.log_error(
'#%d: fields of reg %s (wid=%d) take more bits (%d)' %
(Reg.Lnum, Reg.Name, OrigWid, Wid))
elif (OrigWid > Wid):
logs.log_warning(
'#%d: fields of reg %s (wid=%d) take less bits (%d). consider removing width= from reg definition line'
% (Reg.Lnum, Reg.Name, OrigWid, Wid))
if Reg.Name in Db['splits']:
Db['splitsw'][Reg.Name] = Map
if (OrigReset == 0) and (BuildReset != 0):
Reg.Params['reset'] = BuildReset
elif (OrigReset != 0) and (BuildReset != 0) and (OrigReset !=
BuildReset):
logs.log_error(
"#%d: reg %s has reset value of it's own and also fields. remove one or the other"
% (Reg.Lnum, Reg.Name))
if (OrigWid == 0) and (getPrm(Reg, 'width', 0) == 0):
logs.log_error(
'#%d: reg %s has no width and no fields (defined %s)' %
(Reg.Lnum, Name, list(Db['fields'].keys())))
def executeCommands():
global interactiveWait, Queue
while Queue != []:
Cmd = Queue.pop(0)
if '#' in Cmd: Cmd = Cmd[:Cmd.index('#')]
wrds = Cmd.split()
if len(wrds) == 0:
pass
elif (wrds[0] == '.'):
runcycle()
elif (len(wrds) == 2) and (wrds[0] == 'run'):
for ii in range(int(wrds[1])):
runcycle()
elif (wrds[0] == 'pause'):
logs.log_info('pause on %s' % str(wrds))
return
elif (wrds[0] == 'assert'):
logs.log_info('assert on %s' % str(wrds))
return
elif (wrds[0] == 'till'):
if len(wrds) == 1:
logs.log_error(
'till needs param running|break and optional max run count'
)
else:
What = wrds[1]
if len(wrds) > 2:
Safe = int(wrds[2])
else:
Safe = 1000
if What[0] == 'r':
while (Safe > 0) and (not weAreRunning()):
runcycle()
Safe -= 1
elif What[0] == 'b':
while (Safe > 0) and (not weAreInBreak()):
runcycle()
Safe -= 1
else:
logs.log_error(
'till command accepts "running" "break" parameters, not "%s"'
% (What))
elif (wrds[0] == 'force'):
for ii in range(1, len(wrds) - 1, 2):
Val = wrds[ii + 1]
try:
X = eval(Val)
except:
X = 0
logs.log_error('forcing %s to "%s" failed.' %
(wrds[ii], Val))
Vals = '%x' % X
veri.force(wrds[ii], Vals)
if (wrds[ii] == 'triggers') and (wrds[ii + 1] != '0'):
if apb.queue0 != []:
logs.log_warning(
'triggers toggled while APB queue is not empty. check that all program is loaded by now (len=%d)'
% (len(apb.queue0)))
elif (wrds[0] == 'peek'):
for ii in range(1, len(wrds)):
Val = veri.peek(wrds[ii])
Str = '%s=0x%x' % (wrds[ii], int(Val, 16))
logs.log_info('%s' % Str)
elif (wrds[0] == 'width'):
for ii in range(1, len(wrds)):
Val = veri.width(wrds[ii])
Str = '%s=%d' % (wrds[ii], int(Val))
logs.log_info('%s' % Str)
elif (wrds[0] == 'include'):
try:
File = open(wrds[1])
print('file %s opened ' % wrds[1])
lines = File.readlines()
Queue = lines + Queue
executeCommands()
except:
# traceback.print_last()
# traceback.print_stack()
logs.log_error('failed to include "%s" file' % (wrds[1]))
elif (wrds[0] == 'define'):
Locals[wrds[1]] = eval(wrds[2], Locals)
elif wrds[0] in ['quit', 'exit']:
veri.finish()
sys.exit()
elif wrds[0] in logs.varValues:
Exec = logs.varValues[wrds[0]]
Exec.action(' '.join(wrds[1:]))
elif '.' in wrds[0]:
www = wrds[0].split('.')
if www[0] in imported:
exec(' '.join(wrds), locals(), globals())
else:
print('failed to do \"%s\"' % Cmd)
else:
try:
exec(' '.join(wrds), locals(), globals())
print('exec %s' % str(wrds))
except:
print('failed to do \"%s\"' % Cmd)
def createXml(Module,Db):
Chip = Db['chip']
Items = Db['regs']
Range = Chip.Addr+4
Fout = open('%s/%s.xml'%(Db['dir'],Module),'w')
Fccc = open('%s/%s.h'%(Db['dir'],Module),'w')
Fccc.write(Check.replace('CHECK','%s_'%Module.upper()))
Fccc.write('#define %s_BASEADDR 0x0\n'%(Module.upper()))
Fvcc = open('%s/%s.vh'%(Db['dir'],Module),'w')
Fvcc.write('`define %s_BASEADDR \'h0\n'%(Module.upper()))
Str = HEADER.replace('NAME',Module)
Str = Str.replace('LIBRARY','AutoTalksLib')
Str = Str.replace('BASEADDR','0')
Str = Str.replace('RANGE','%x'%Range)
Fout.write(Str)
BusWidth = Db['chip'].Params['width']
Pref = ''
if 'pref' in Db['chip'].Params:
Pref = Db['chip'].Params['pref']
for Item in Items:
Usable=True
if Item.Kind=='ram':
Acc = 'ram'
Amount = Item.Params['depth']
elif Item.Kind=='gap':
Usable=False
elif Item.Kind=='field':
Usable=False
elif Item.Kind=='external':
Usable=False
else:
logs.mustKey(Item.Params,'access','#%d:'%Item.Lnum)
if 'access' in Item.Params:
Acc = Item.Params['access']
Amount = 0
if Usable:
Wid = Item.Params['width']
Reg = Item.Params['names'][0]
if 'desc' in Item.Params:
Item.Params['description'] = Item.Params['desc']
if 'description' not in Item.Params:
Desc = 'DESC NOT GIVEN'
logs.log_warning('#%d: description of %s not given'%(Item.Lnum,Reg))
else:
Desc = Item.Params['description']
if 'reset' not in Item.Params:
Reset = 0
else:
Reset = Item.Params['reset']
Addr = Item.Addr
# Fout.write('item %s %x %s\n'%(Item.Kind,Item.Addr,Item.Params))
if Wid<=32:
writeItem(Db,Item,Fout,Module,Acc,Addr,Wid,Reset,Desc,Reg,Amount)
else:
Acc0 = Acc
Acc = Acc.replace('_pulse','')
Run = 0
while Wid>32:
writeItem(Db,Item,Fout,Module,Acc,Addr,32,Reset,Desc,Reg+'_%d'%Run,Amount)
Addr += 4
Run += 1
Wid -= 32
writeItem(Db,Item,Fout,Module,Acc,Addr,Wid,Reset,Desc,Reg+'_%d'%Run,Amount)
Addr = Item.Addr
Wid = Item.Params['width']
if (Wid>BusWidth)and(Wid<=(BusWidth*2)):
BusBytes = int(BusWidth/8)
Fccc.write('#define %sADDR_%-50s (%s_BASEADDR+0x%x)\n'%(Pref,Reg.upper()+'_LO',Module.upper(),Addr))
Fccc.write('#define %sADDR_%-50s (%s_BASEADDR+0x%x)\n'%(Pref,Reg.upper()+'_HI',Module.upper(),Addr+BusBytes))
Fvcc.write('`define %sADDR_%-50s \'h%x\n'%(Pref,Reg.upper()+'_LO',Addr))
Fvcc.write('`define %sADDR_%-50s \'h%x\n'%(Pref,Reg.upper()+'_HI',Addr+BusBytes))
else:
Fccc.write('#define %sADDR_%-50s (%s_BASEADDR+0x%x)\n'%(Pref,Reg.upper(),Module.upper(),Addr))
Fvcc.write('`define %sADDR_%-50s \'h%x\n'%(Pref,Reg.upper(),Addr))
Fccc.write('\n\n#endif\n')
Fccc.close()
Fout.write(TRAILER)
Fout.close()
def runNewRtl(Mod):
Insts = list(Mod.insts.keys())
Alwayses0 = {}
Alwayses1 = {}
Alwayses2 = {}
for Inst in Insts:
Obj = Mod.insts[Inst]
Type = Obj.Type
if 'delay' in Obj.params:
Dly = Obj.params['delay']
Dly = [(Dly, Dly)]
else:
Dly = ''
if Type.startswith('nandi'):
O, Ins = typicalConns(Obj.conns, '&', True)
Mod.hard_assigns.append((O, ('~', Ins), '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('andi'):
O, Ins = typicalConns(Obj.conns, '&', True)
Mod.hard_assigns.append((O, Ins, '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('nand'):
O, Ins = typicalConns(Obj.conns, '&')
Mod.hard_assigns.append((O, ('~', Ins), '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('and'):
O, Ins = typicalConns(Obj.conns, '&')
Mod.hard_assigns.append((O, Ins, '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('nor'):
O, Ins = typicalConns(Obj.conns, '|')
Mod.hard_assigns.append((O, ('~', Ins), '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('or'):
O, Ins = typicalConns(Obj.conns, '|')
Mod.hard_assigns.append((O, Ins, '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('xor'):
O, Ins = typicalConns(Obj.conns, '^')
Mod.hard_assigns.append((O, Ins, '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('less'):
O, Ins = typicalConns(Obj.conns, '^')
Mod.hard_assigns.append((O, ('<', Ins[1], Ins[2]), '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('more'):
O, Ins = typicalConns(Obj.conns, '^')
Mod.hard_assigns.append((O, ('>', Ins[1], Ins[2]), '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('xnor'):
O, Ins = typicalConns(Obj.conns, '^')
Mod.hard_assigns.append((O, ('~', Ins), '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('inv'):
O, Ins = typicalConns(Obj.conns, '&')
Mod.hard_assigns.append((O, ('~', Ins), '', Dly))
Mod.insts.pop(Inst)
elif Type.startswith('buf'):
O, Ins = typicalConns(Obj.conns, '&')
Mod.hard_assigns.append((O, Ins, '', Dly))
equalizeWidth(Mod, O, Ins[0])
Mod.insts.pop(Inst)
elif Type == 'mux2':
ensureExists(Obj, Inst, 'i0 i1 s o')
i0 = Obj.conns['i0']
i1 = Obj.conns['i1']
s = Obj.conns['s']
O = Obj.conns['o']
Mod.hard_assigns.append((O, ('question', s, i1, i0), '', Dly))
Mod.insts.pop(Inst)
elif Type == 'mux4':
ensureExists(Obj, Inst, 'i0 i1 i2 i3 s0 s1 o')
i0 = Obj.conns['i0']
i1 = Obj.conns['i1']
i2 = Obj.conns['i2']
i3 = Obj.conns['i3']
s0 = Obj.conns['s0']
s1 = Obj.conns['s1']
O = Obj.conns['o']
Mod.hard_assigns.append(
(O, ('question', s1, ('question', s0, i3, i2),
('question', s0, i1, i0)), '', Dly))
Mod.insts.pop(Inst)
elif Type == 'flop':
ensureExists(Obj, Inst, 'ck d q')
Ck = Obj.conns['ck']
D = Obj.conns['d']
Q = Obj.conns['q']
Mod.add_net(Q, 'reg', 0)
if Ck not in Alwayses0: Alwayses0[Ck] = []
Alwayses0[Ck].append((Q, D))
equalizeWidth(Mod, Q, D)
Mod.insts.pop(Inst)
elif Type == 'dffr':
ensureExists(Obj, Inst, 'ck d q rn')
Ck = Obj.conns['ck']
D = Obj.conns['d']
Q = Obj.conns['q']
RN = Obj.conns['rn']
Mod.add_net(Q, 'reg', 0)
if 'qn' in Obj.conns:
QN = Obj.conns['qn']
if (QN != ''):
Mod.add_net(QN, 'wire', 0)
Mod.hard_assigns.append((QN, ['~', Q], '', ''))
if (Ck, RN) not in Alwayses1: Alwayses1[(Ck, RN)] = []
Alwayses1[(Ck, RN)].append((Q, D, 0))
equalizeWidth(Mod, Q, D)
if ('qn' in Obj.conns) and (QN != ''):
equalizeWidth(Mod, QN, D)
Mod.insts.pop(Inst)
elif Type == 'dffs':
ensureExists(Obj, Inst, 'ck d q sn')
Ck = Obj.conns['ck']
D = Obj.conns['d']
Q = Obj.conns['q']
SN = Obj.conns['sn']
Mod.add_net(Q, 'reg', 0)
if (Ck, SN) not in Alwayses1: Alwayses1[(Ck, SN)] = []
Alwayses1[(Ck, SN)].append((Q, D, 1))
if 'qn' in Obj.conns:
QN = Obj.conns['qn']
if (QN != ''):
Mod.add_net(QN, 'wire', 0)
Mod.hard_assigns.append((QN, ['~', Q], '', ''))
equalizeWidth(Mod, Q, D)
if ('qn' in Obj.conns) and (QN != ''):
equalizeWidth(Mod, QN, D)
Mod.insts.pop(Inst)
elif list(Obj.conns.keys()) != []:
pass
else:
logs.log_warning('%s ignored for rtl verilog %s %s' %
(Type, Inst, Obj.conns))
for Ck in Alwayses0:
List = Alwayses0[Ck]
List2 = ['list']
for Q, D in List:
List2.append(('<=', Q, D))
Mod.alwayses.append((('edge', 'posedge', Ck), List2, 'always'))
for Ck, RN in Alwayses1:
List = Alwayses1[(Ck, RN)]
List2 = ['list']
for Q, D, _ in List:
List2.append(('<=', Q, D))
ListRst = ['list']
for Q, _, Df in List:
ListRst.append(('<=', Q, Df))
Mod.alwayses.append(
(('list', ('edge', 'posedge', Ck), ('edge', 'negedge', RN)),
['ifelse', ('!', RN), ListRst, List2], 'always'))
def __use_command_wrds(wrds):
if len(wrds) == 0:
return
if wrds[0] == 'history':
for LL in Glbs.history:
print(LL)
return
else:
Glbs.history.append(' '.join(wrds))
Root = Glbs.get_context('root')
if wrds[0] in Glbs.imported:
Glbs.imported[wrds[0]](wrds)
elif wrds[0] in ['import']:
import_command(wrds[1])
# Fname = os.path.expanduser(wrds[1])
# Fname = os.path.abspath(Fname)
# if not Fname.endswith('.py'):
# logs.log_error('import expect filename ending with .py')
# else:
# Command,Function = my_importing(Fname)
# if Command:
# Glbs.imported[Command] = Function
elif wrds[0] in ['source', 'include']:
Fname = os.path.expanduser(wrds[1])
Fname = os.path.abspath(Fname)
try:
Lines = open(Fname).readlines()
for line in Lines:
wrds0 = line.split()
use_command_wrds(wrds0)
except:
logs.log_error('failed to open include file "%s" ' % Fname)
X = sys.exc_info()
traceback.print_exception(etype=X[0], value=X[1], tb=X[2])
elif wrds[0] in ['quit', 'exit']:
Glbs.details[Root].touched('Q')
Glbs.pleaseExit = True
Glbs.finished = True
stopRunning()
sys.exit()
elif wrds[0] in ['zpicslib', 'picslib']:
Dirs = Glbs.get_context('pics_lib')
if type(Dirs) is str:
Dirs = [Dirs]
for Wrd in wrds[1:]:
Fname = os.path.expanduser(Wrd)
Fname = os.path.abspath(Fname)
if os.path.exists(Fname):
if Fname not in Dirs:
Dirs.append(Fname)
else:
logs.log_errorprint(
'Failed to add "%s" to legal paths, as it cannot be opened'
% Fname)
Glbs.set_context('pics_lib', Dirs)
print('PICSLIBS: %s' % str(Dirs))
elif wrds[0] == 'rename':
New = wrds[1]
Glbs.details[New] = copy.deepcopy(Glbs.details[Root])
Glbs.details[New].Module = New
Glbs.set_context('root', New)
Glbs.graphicsChanged = True
Glbs.undoStack = []
Glbs.redoStack = []
elif wrds[0] == 'Save':
wrds[0] = 'save'
__use_command_wrds(wrds)
__use_command_wrds(['print'])
__use_command_wrds(['verilog'])
__use_command_wrds(['pickle'])
__use_command_wrds(['picture'])
elif wrds[0] == 'pickle':
Schem = Glbs.details[Root]
Fout = open('%s.pickle' % Root, 'wb')
logs.log_info('pickle %s' % Schem)
pickle.dump(Schem, Fout)
Fout.close()
elif wrds[0] == 'save':
if len(wrds) > 1:
WW = wrds[1].split('/')
if WW[-1].startswith(Root):
if '.zdraw' not in WW[1]:
Fname = wrds[1] + '.zdraw'
Fname = wrds[1]
else:
Fname = wrds[1] + '/' + Root + '.zdraw'
Fname = os.path.expanduser(Fname)
Fname = os.path.abspath(Fname)
elif Root in Glbs.associated_dir:
Fname = '%s/%s.zdraw' % (Glbs.associated_dir[Root], Root)
else:
Fname = '%s.zdraw' % Root
logs.log_info('saving %s to %s file' % (Root, Fname))
try:
File = open(Fname, 'w')
Glbs.details[Root].save(File)
File.close()
Glbs.details[Root].touched(False)
except:
logs.log_info('Failed to open "%s" for saving' % Fname)
elif wrds[0] == 'change':
List = list(Glbs.details.keys())
List.sort()
if len(wrds) == 1:
logs.log_info('available schematics: %s' % ' '.join(List))
elif (wrds[1] in List):
Glbs.set_context('root', wrds[1])
Glbs.graphicsChanged = True
else:
logs.log_error('"%s" is not loaded. use new to open new drawing' %
wrds[1])
elif wrds[0] == 'delete':
if (Root != 'opening'):
Glbs.details.pop(Root)
Glbs.set_context('root', 'opening')
Glbs.graphicsChanged = True
elif wrds[0] == 'V':
Glbs.set_contect('useVectorText',
not Glbs.get_context('useVectorText'))
Glbs.graphicsChanged = True
elif wrds[0] in ['plot', 'print']:
dbase.postscript_current()
elif 'new' in wrds[0]:
if len(wrds) != 2:
logs.log_error('new needs schematic name')
else:
Root = wrds[1]
Glbs.set_context('root', Root)
Glbs.details[Root] = dbase.DetailClass(Root)
Glbs.graphicsChanged = True
Glbs.undoStack = []
Glbs.redoStack = []
elif 'load' in wrds[0]:
if len(wrds) == 1:
logs.log_info('loaded schematics: %s' %
str(list(Glbs.details.keys())))
# logs.log_info('loaded pictures: %s'%str(list(Glbs.pictures.keys())))
else:
load_schematics(wrds[1])
elif wrds[0] == 'text':
Glbs.adding_text_queue.extend(wrds[1:])
elif 'add' in wrds[0]:
List = dbase.findMatches('')
if len(wrds) == 1:
logs.log_info('loaded pictures: %s' % str(List))
else:
for Wrd in wrds[1:]:
if Wrd in List:
Glbs.adding_queue.append(Wrd)
else:
Match = dbase.findMatches(Wrd)
if len(Match) == 1:
Glbs.adding_queue.extend(Match)
else:
logs.log_error(
'add of "%s" failed,. not found or found several: "%s"'
% (Wrd, str(Match)))
elif 'name' in wrds[0]:
Glbs.paramName = 'name'
Glbs.params_queue.extend(wrds[1:])
elif 'param' == wrds[0]:
Glbs.paramName = wrds[1]
Glbs.params_queue.extend(wrds[2:])
elif 'spice' in wrds[0]:
Root = Glbs.get_context('root')
Fname = '%s.cir' % (Root)
File = open(Fname, 'w')
logs.log_info('writing spice file "%s.cir"' % Root)
GG = connectivityClass(Glbs, Root)
GG.dumpSpice(File)
File.close()
elif wrds[0] in ['zlib', 'picture']:
if len(wrds) == 1:
Fname = '%s.zpic' % (Root)
elif len(wrds) >= 1:
Fname = os.path.expanduser(Fname)
Fname = os.path.abspath(Fname)
ww = Fname.split('/')
if ww[-1] == Root:
Fname = Fname + '.zpic'
ww = Fname.split('/')
if ww[-1] not in [Root, Root + '.zpic']:
Fname = Fname + '/' + Root + '.zpic'
try:
File = open(Fname, 'w')
except:
log_error('failed to open zpic file for writing "%s" ' % Fname)
File = False
if File:
pictify.pictify(Glbs, Root, File)
elif ('dump' in wrds[0]) or ('verilog' in wrds[0]) or (
'rtl' in wrds[0]) or ('user' in wrds[0]):
Rtl = 'rtl' in wrds[0]
User = '******' in wrds[0]
if len(wrds) == 1:
Root = Glbs.get_context('root')
Fname = '%s.v' % (Root)
File = open(Fname, 'w')
logs.log_info('writing verilog file "%s.v"' % Root)
GG = connectivityClass(Glbs, Root)
GG.dumpVerilog(File, Rtl, User)
File.close()
elif len(wrds) == 2:
Fname = wrds[1]
File = open(Fname, 'w')
Root = Glbs.get_context('root')
GG = connectivityClass(Glbs, Root)
GG.dumpVerilog(File, Rtl, User)
File.close()
elif len(wrds) == 3:
Fname = wrds[2]
File = open(Fname, 'w')
if wrds[1] == '*':
for Name in Glbs.details:
GG = connectivityClass(Glbs, Root)
GG.dumpVerilog(File, Rtl, User)
else:
GG = connectivityClass(Glbs, wrds[1])
GG.dumpVerilog(File, Rtl, User)
File.close()
elif ('sys' == wrds[0]):
os.system('%s\n' % (' '.join(wrds[1:])))
elif 'ls' in wrds[0]:
if len(wrds) > 1:
Dir = wrds[1]
else:
Dir = '.'
if not os.path.exists(Dir):
logs.log_warning('no such directory "%s"' % Dir)
return
LL = os.listdir(Dir)
L1 = []
L2 = []
for Fname in LL:
if ('.zdraw' in Fname):
L1.append(Fname)
elif ('.zpic' in Fname):
L2.append(Fname)
elif ('.zlib' in Fname):
L2.append(Fname)
for Cell in L1 + L2:
Glbs.listed[Cell] = Dir
logs.log_info('schematics in "%s" %s' % (Dir, L1))
logs.log_info('pictures in "%s" %s' % (Dir, L2))
elif (len(wrds) == 3) and (wrds[1] == '='):
if wrds[0] == 'useVectorText':
Glbs.set_context('useVectorText', eval(wrds[2]))
Glbs.graphicsChanged = True
elif wrds[0] == 'font':
OKfonts = pygame.font.get_fonts()
Font = wrds[2]
if Font in OKfonts:
Glbs.set_context('font', Font)
else:
logs.log_error('font "%s" not in fonts:\n %s' %
(Font, OKfonts))
elif wrds[0] in ['pics_lib']:
Was = Glbs.get_context(wrds[0])
X = makenum(wrds[2])
if type(X) is str:
Was.append(X)
elif type(X) is list:
Was.extend(X)
Glbs.set_context(wrds[0], Was)
else:
if wrds[0] not in Glbs.contexts:
logs.log_info('defining new context param "%s" ' % wrds[0])
Glbs.set_context(wrds[0], makenum(wrds[2]))
elif (wrds[0] == 'variables'):
for Key in Glbs.contexts:
print(Key, Glbs.contexts[Key])
elif 'help' in wrds[0]:
if len(wrds) == 1:
logs.log_info(helpString.helpString)
else:
List = helpString.helpString.split('\n')
for Str in List:
if wrds[1] in Str:
logs.log_info(Str)
elif matchesCommand(wrds[0]):
Comm = matchesCommand(wrds[0])
wrds[0] = Comm
use_command_wrds(wrds)
else:
logs.log_error('dont know to %s' % wrds)