def main():
lsim = lsimpy.LSimContext()
lsim.add_folder("examples", "../../examples")
sim = lsim.sim()
if (not lsim.load_user_library("examples/shifter.lsim")):
print("Unable to load circuit\n")
exit(-1)
circuit_desc = lsim.user_library().circuit_by_name('barrel_8bit')
pin_SHL = circuit_desc.port_by_name("Shl")
pin_A = [circuit_desc.port_by_name(f"A[{i:}]") for i in range(0,8)]
pin_S = [circuit_desc.port_by_name(f"S[{i:}]") for i in range(0,4)]
pin_Y = [circuit_desc.port_by_name(f"Y[{i:}]") for i in range(0,8)]
circuit = circuit_desc.instantiate(sim)
sim.init()
for shl in range(0, 2):
circuit.write_pin(pin_SHL, lsimpy.ValueTrue if shl else lsimpy.ValueFalse)
for a in range (0, 2**8):
circuit.write_byte(pin_A, a)
for s in range (0, 2**3):
circuit.write_nibble(pin_S, s)
sim.run_until_stable(5)
result = circuit.read_byte(pin_Y)
expected = (a << s if shl else a >> s) & (2**8-1)
CHECK(result, expected, "SHL({}), A({}), S({})".format(shl,a,s))
print_stats()
def main():
lsim = lsimpy.LSimContext()
lsim.add_folder("examples", "../../examples")
sim = lsim.sim()
if (not lsim.load_user_library("examples/compare.lsim")):
print("Unable to load circuit\n")
exit(-1)
circuit_desc = lsim.user_library().circuit_by_name("comp_8bit")
pin_A = [circuit_desc.port_by_name(f"A[{i:}]") for i in range(0,8)]
pin_B = [circuit_desc.port_by_name(f"B[{i:}]") for i in range(0,8)]
pin_LT = circuit_desc.port_by_name("LT")
pin_EQ = circuit_desc.port_by_name("EQ")
pin_GT = circuit_desc.port_by_name("GT")
circuit = circuit_desc.instantiate(sim)
sim.init()
for a in range(0, 2**8):
circuit.write_byte(pin_A, a)
for b in range(0, 2**8):
circuit.write_byte(pin_B, b)
sim.run_until_stable(5)
expected_LT = lsimpy.ValueTrue if a < b else lsimpy.ValueFalse
expected_EQ = lsimpy.ValueTrue if a == b else lsimpy.ValueFalse
expected_GT = lsimpy.ValueTrue if a > b else lsimpy.ValueFalse
CHECK(circuit.read_pin(pin_LT), expected_LT, "{} < {}".format(a, b))
CHECK(circuit.read_pin(pin_EQ), expected_EQ, "{} == {}".format(a, b))
CHECK(circuit.read_pin(pin_GT), expected_GT, "{} > {}".format(a, b))
print_stats()
def main():
lsim = lsimpy.LSimContext()
lsim.add_folder("examples", "../../examples")
if (not lsim.load_user_library("examples/cpu_8bit/lib_counter.lsim")):
print("Unable to load circuit\n")
exit(-1)
test_bin_counter_4b(lsim)
test_bin_counter_8b(lsim)
print_stats()
def main():
lsim = lsimpy.LSimContext()
lsim.add_folder("examples", "../../examples")
if (not lsim.load_user_library("examples/cpu_8bit/lib_memory.lsim")):
print("Unable to load circuit\n")
exit(-1)
test_mem_cell(lsim)
test_ram_8byte(lsim)
test_ram_64byte(lsim)
print_stats()
def __init__(self, name, word_size, word_count):
assert word_count > 0 and ((word_count & (word_count - 1)) == 0), "word_count should be a power of two"
assert word_size in [8, 16, 32], "word_size should be 8/16/32"
assert word_count * word_size / 8 <= 512 * 1024, "ROM is limited to a maximum of 512k bytes"
self.lsim = lsimpy.LSimContext()
self.lsim.add_folder("examples", "../../examples")
self.name = name
self.word_size = word_size
self.word_count = word_count
# use word_count as a guide to set initial number of adress lines
self.addr_lines = int(math.log2(self.word_count))
# set number of columns depending on word size (always 128 bits wide)
self.col_count = int(128 / self.word_size) # number of colums
self.col_lines = int(math.log2(self.col_count)) # address lines used for columns
# set number of rows as required, at a mininum 2 (smallest demuxer) and maximum 6 (largest demuxer)
self.row_lines = max(min(6, self.addr_lines - self.col_lines), 2) # address lines used for rows
self.row_count = 2**self.row_lines
# set number of segments as required
self.segment_lines = max(self.addr_lines - self.col_lines - self.row_lines, 0)
self.segment_count = 2**self.segment_lines
# total number of address lines might be larger than original guideline for small data sets
self.addr_lines = self.col_lines + self.row_lines + self.segment_lines
# prepare multidimensional array to hold 'data' pull low gates
self.data = [[[[] for r in range(self.row_count)] for c in range(self.col_count)] for s in range(self.segment_count)]
# precalculate address calculation constants
self.row_mask = (1 << self.row_lines) - 1
self.col_shift = self.row_lines
self.col_mask = ((1 << self.col_lines) - 1) << self.col_shift
self.seg_shift = self.row_lines + self.col_lines
self.seg_mask = ((1 << self.segment_lines) - 1) << self.seg_shift
print(f"segments = {self.segment_count:} columns = {self.col_count:} rows = {self.row_count:}")
self.segments = []
def main():
lsim = lsimpy.LSimContext()
sim = lsim.sim()
if (not lsim.load_user_library("../../examples/adder.lsim")):
print("Unable to load circuit\n")
exit(-1)
circuit_desc = lsim.user_library().circuit_by_name("adder_4bit")
pin_Ci = circuit_desc.port_by_name("Ci")
pin_A = [circuit_desc.port_by_name(f"A{i:}") for i in range(0, 4)]
pin_B = [circuit_desc.port_by_name(f"B{i:}") for i in range(0, 4)]
pin_Y = [circuit_desc.port_by_name(f"Y{i:}") for i in range(0, 4)]
pin_Co = circuit_desc.port_by_name("Co")
circuit = circuit_desc.instantiate(sim)
sim.init()
for ci in [0, 1]:
circuit.write_pin(pin_Ci,
lsimpy.ValueTrue if ci else lsimpy.ValueFalse)
for a in range(0, 2**4):
circuit.write_nibble(pin_A, a)
for b in range(0, 2**4):
circuit.write_nibble(pin_B, b)
sim.run_until_stable(5)
expected_y = a + b + ci
expected_co = 0
if expected_y >= 2**4:
expected_co = 1
expected_y = expected_y - 2**4
CHECK(circuit.read_pin(pin_Co), expected_co,
"{} + {} + {}".format(ci, a, b))
CHECK(circuit.read_nibble(pin_Y), expected_y,
"{} + {} + {}".format(ci, a, b))
print_stats()
def main():
global pins_A, pins_B, pins_Y, pins_Instr, pin_CE, pin_OE
lsim = lsimpy.LSimContext()
lsim.add_folder("examples", "../../examples")
sim = lsim.sim()
if (not lsim.load_user_library("examples/cpu_8bit/alu.lsim")):
print("Unable to load circuit\n")
exit(-1)
circuit_desc = lsim.user_library().circuit_by_name("alu")
pins_A = [circuit_desc.port_by_name(f"A[{i:}]") for i in range(0, 8)]
pins_B = [circuit_desc.port_by_name(f"B[{i:}]") for i in range(0, 8)]
pins_Y = [circuit_desc.port_by_name(f"Y[{i:}]") for i in range(0, 8)]
pins_Instr = [
circuit_desc.port_by_name(f"Instr[{i:}]") for i in range(0, 4)
]
pin_CE = circuit_desc.port_by_name("CE")
pin_OE = circuit_desc.port_by_name("OE")
circuit = circuit_desc.instantiate(sim)
sim.init()
circuit.write_port("CE", lsimpy.ValueFalse)
circuit.write_port("OE", lsimpy.ValueFalse)
circuit.write_nibble(pins_Instr, 0)
circuit.write_byte(pins_A, 0)
circuit.write_byte(pins_B, 0)
check_addition(circuit, sim)
check_subtraction(circuit, sim)
check_shift_right(circuit, sim)
check_shift_left(circuit, sim)
check_and(circuit, sim)
check_or(circuit, sim)
check_xor(circuit, sim)
print_stats()
#!/usr/bin/env python3
import lsimpy
from bench_utils import *
lsim = lsimpy.LSimContext()
HIGH = lsimpy.ValueTrue
LOW = lsimpy.ValueFalse
NONE = lsimpy.ValueUndefined
def test_sr_latch():
truth_table = [[{
'R': HIGH,
'S': LOW
}, {
'Q': LOW,
'/Q': HIGH
}], [{
'R': LOW,
'S': LOW
}, {
'Q': LOW,
'/Q': HIGH
}], [{
'R': LOW,
'S': HIGH
}, {
'Q': HIGH,
'/Q': LOW