def connectCPU(self, cpu):
"""Connect the CPU itb and dtb to the cache
Note: This creates a new crossbar
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.master
cpu.mmu.connectWalkerPorts(self.mmubus.slave, self.mmubus.slave)
def incorporate_cache(self, board: AbstractBoard) -> None:
# Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports)
for cntr in board.get_memory().get_memory_controllers():
cntr.port = self.membus.mem_side_ports
self.l1icaches = [
L1ICache(size=self._l1i_size)
for i in range(board.get_processor().get_num_cores())
]
self.l1dcaches = [
L1DCache(size=self._l1d_size)
for i in range(board.get_processor().get_num_cores())
]
self.l2buses = [
L2XBar() for i in range(board.get_processor().get_num_cores())
]
self.l2caches = [
L2Cache(size=self._l2_size)
for i in range(board.get_processor().get_num_cores())
]
# ITLB Page walk caches
self.iptw_caches = [
MMUCache(size='8KiB')
for _ in range(board.get_processor().get_num_cores())
]
# DTLB Page walk caches
self.dptw_caches = [
MMUCache(size='8KiB')
for _ in range(board.get_processor().get_num_cores())
]
if board.has_coherent_io():
self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side)
self.l1icaches[i].mem_side = self.l2buses[i].cpu_side_ports
self.l1dcaches[i].mem_side = self.l2buses[i].cpu_side_ports
self.iptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports
self.dptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports
self.l2buses[i].mem_side_ports = self.l2caches[i].cpu_side
self.membus.cpu_side_ports = self.l2caches[i].mem_side
cpu.connect_walker_ports(self.iptw_caches[i].cpu_side,
self.dptw_caches[i].cpu_side)
if get_runtime_isa() == ISA.X86:
int_req_port = self.membus.mem_side_ports
int_resp_port = self.membus.cpu_side_ports
cpu.connect_interrupt(int_req_port, int_resp_port)
else:
cpu.connect_interrupt()
def connectCPU(self, cpu):
"""Connect the CPU itb and dtb to the cache
Note: This creates a new crossbar
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.master
for tlb in [cpu.itb, cpu.dtb]:
self.mmubus.slave = tlb.walker.port
