name = "ShiftRegister" IO = ["I", m.In(T), "O", m.Out(T)] + m.ClockInterface() @classmethod def definition(io): regs = [Register4() for _ in range(N)] m.wireclock(io, regs) m.wire(io.I, getattr(regs[0], "in")) m.fold(regs, foldargs={"in":"out"}) m.wire(regs[-1].out, io.O) # In[2]: from magma.backend.verilog import compile as compile_verilog print(compile_verilog(ShiftRegister)) # In[3]: from magma.simulator import PythonSimulator from magma.bit_vector import BitVector simulator = PythonSimulator(ShiftRegister, clock=ShiftRegister.CLK) outputs = [] for i in range(0, 1 << N): simulator.set_value(ShiftRegister.I, BitVector(i, N)) for j in range(2): simulator.step() simulator.evaluate()
@classmethod def definition(io): # Generate the sum _sum = io.a ^ io.b ^ io.cin wire(_sum, io.out) # Generate the carry carry = (io.a & io.b) | (io.b & io.cin) | (io.a & io.cin) wire(carry, io.cout) # In[2]: from magma.backend.verilog import compile as compile_verilog print(compile_verilog(FullAdder)) # In[3]: from magma.simulator.python_simulator import testvectors test_vectors = [[0, 0, 0, 0, 0], [0, 0, 1, 1, 0], [0, 1, 0, 1, 0], [0, 1, 1, 0, 1], [1, 0, 0, 1, 0], [1, 0, 1, 0, 1], [1, 1, 0, 0, 1], [1, 1, 1, 1, 1]] tests = testvectors(FullAdder) print(tests) print("Success" if tests == test_vectors else "Failure") # In[4]:
rxmod = RXMOD() txmod = TXMOD() databuf = Register(8, has_ce=True) wire(databuf.CLK, io.CLK) wire(databuf.CE, txmod.ready | rxmod.valid) wire(databuf.I, rxmod.data) databufValid = Register(1, has_ce=True) wire(databufValid.CLK, io.CLK) wire(databufValid.CE, txmod.ready | rxmod.valid) wire(databufValid.I, bits(rxmod.valid)) wire(rxmod.RX, io.RX) wire(rxmod.CLK, io.CLK) wire(txmod.TX, io.TX) wire(txmod.CLK, io.CLK) #wire(txmod.data,databuf.O) wire(bits(txmod.valid), databufValid.O) process = Process() wire(databuf.O, process.I) wire(process.O, txmod.data) from magma.backend.verilog import compile as compile_verilog print(compile_verilog(Main)) compile("magtest", Main, include_coreir=True)
name = "ResetShiftRegister" IO = ["I", In(T), "reset", In(Bit), "O", Out(T)] + ClockInterface() @classmethod def definition(io): regs = [Register4().reset(io.reset) for _ in range(4)] wireclock(io, regs) wire(io.I, getattr(regs[0], "in")) fold(regs, foldargs={"in": "out"}) wire(regs[-1].out, io.O) # In[2]: from magma.backend.verilog import compile as compile_verilog print(compile_verilog(ResetShiftRegister)) # In[3]: from magma.simulator import PythonSimulator from magma.bit_vector import BitVector simulator = PythonSimulator(ResetShiftRegister, clock=ResetShiftRegister.CLK) outputs = [] simulator.set_value(ResetShiftRegister.reset, True) for i in range(0, 1 << N): simulator.set_value(ResetShiftRegister.I, BitVector(i, N)) for j in range(2): if i == 9: if j == 0:
is_op3 = io.opcode == uint(3, n=2) op0_out = io.a + io.b op1_out = io.a - io.b op2_out = io.a op3_out = io.b wire( io.out, one_hot_mux([is_op0, is_op1, is_op2, is_op3], [op0_out, op1_out, op2_out, op3_out])) # In[2]: from magma.backend.verilog import compile as compile_verilog print(compile_verilog(SimpleALU)) # In[3]: from magma.simulator import PythonSimulator from magma.bit_vector import BitVector simulator = PythonSimulator(SimpleALU) simulator.set_value(SimpleALU.a, BitVector(3, num_bits=4)) simulator.set_value(SimpleALU.b, BitVector(2, num_bits=4)) simulator.set_value(SimpleALU.opcode, BitVector(0, num_bits=2)) simulator.evaluate() assert simulator.get_value(SimpleALU.out) == BitVector(3 + 2, num_bits=4) simulator.set_value(SimpleALU.a, BitVector(3, num_bits=4)) simulator.set_value(SimpleALU.b, BitVector(2, num_bits=4))
def definition(io): rxmod = RXMOD() txmod = TXMOD() databuf = Register(8, has_ce=True) wire(databuf.CLK,io.CLK) wire(databuf.CE,txmod.ready | rxmod.valid) wire(databuf.I, rxmod.data) databufValid = Register(1, has_ce=True) wire(databufValid.CLK,io.CLK) wire(databufValid.CE,txmod.ready | rxmod.valid) wire(databufValid.I,bits(rxmod.valid)) wire(rxmod.RX,io.RX) wire(rxmod.CLK,io.CLK) wire(txmod.TX,io.TX) wire(txmod.CLK,io.CLK) #wire(txmod.data,databuf.O) wire(bits(txmod.valid),databufValid.O) process = Process() wire(databuf.O,process.I) wire(process.O,txmod.data) from magma.backend.verilog import compile as compile_verilog print(compile_verilog(Main)) compile("magtest",Main,include_coreir=True)