def gen_model(real_type):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_analog_output('g')
# bind expression to internal signal
m.add_digital_param('param_a')
m.add_digital_param('param_b')
m.add_digital_param('param_c', width=2, signed=True)
m.add_digital_param('param_d', width=2, signed=True)
m.add_real_param('param_e')
m.add_real_param('param_f')
# create state signals
m.add_digital_state('sig1', init=m.param_a)
m.add_digital_state('sig2', init=m.param_c, width=2, signed=True)
m.add_analog_state('sig3', init=m.param_e, range_=25)
# create main logic
m.set_next_cycle(m.sig1, m.param_b, clk=m.clk, rst=m.rst)
m.set_next_cycle(m.sig2, m.param_d, clk=m.clk, rst=m.rst)
m.set_next_cycle(m.sig3, m.param_f, clk=m.clk, rst=m.rst)
# sum signals to output
m.set_this_cycle(m.g, m.sig1 + m.sig2 + m.sig3)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(tau, real_type):
# create mixed-signal model
m = MixedSignalModel('model', build_dir=BUILD_DIR, real_type=real_type)
# define I/O
x = m.add_analog_input('x')
dt = m.add_analog_input('dt')
y = m.add_analog_output('y')
clk = m.add_digital_input('clk')
rst = m.add_digital_input('rst')
# create function
func = m.make_function(lambda t: np.exp(-t / tau),
domain=[0, 1e-6],
order=1)
# apply function
f = m.set_from_sync_func('f', func, dt, clk=clk, rst=rst)
# update output
x_prev = m.cycle_delay(x, 1, clk=clk, rst=rst)
y_prev = m.cycle_delay(y, 1, clk=clk, rst=rst)
m.set_this_cycle(y, f * y_prev + (1 - f) * x_prev)
# write the model
return m.compile_to_file(VerilogGenerator())
def gen_model(real_type):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_analog_input('a')
m.add_analog_input('b')
m.add_digital_output('c')
# bind expression to internal signal
m.set_this_cycle(m.c, m.a > m.b)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model():
# declare model I/O
m = MixedSignalModel('model')
m.add_digital_input('a', width=63, signed=True)
m.add_digital_input('b', width=63, signed=True)
m.add_digital_output('c', width=64, signed=True)
# assign expression to output
m.bind_name('d', m.a - m.b)
m.set_this_cycle(m.c, m.d)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model():
# declare module
m = MixedSignalModel('model')
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_digital_input('seed', width=32)
m.add_digital_output('out', width=32)
# sum signals to output
m.set_this_cycle(m.out, mt19937(clk=m.clk, rst=m.rst, seed=m.seed))
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(width, init, real_type):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_digital_output('out', width=width)
# bind expression to internal signal
lfsr = m.lfsr_signal(width, clk=m.clk, rst=m.rst, init=init)
m.set_this_cycle(m.out, lfsr)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(n, vn, vp, dt, real_type):
# declare model I/O
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_digital_input('d_in', width=n, signed=True)
m.add_analog_output('a_out')
# compute expression for DAC output
expr = ((m.d_in + (2**(n - 1))) / ((2**n) - 1)) * (vp - vn) + vn
# assign expression to output
m.set_this_cycle(m.a_out, expr)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(n, vn, vp, dt, real_type):
# declare model I/O
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('a_in')
m.add_digital_output('d_out', width=n, signed=True)
# compute expression for ADC output as an unclamped, real number
expr = ((m.a_in - vn) / (vp - vn) * ((2**n) - 1)) - (2**(n - 1))
# clamp to ADC range
clamped = clamp_op(expr, -(2**(n - 1)), (2**(n - 1)) - 1)
# assign expression to output
m.set_this_cycle(m.d_out, to_sint(clamped, width=n))
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file