def test_add_cout_one():
args = ['I0', In(Bits(1)), 'I1', In(Bits(1)), 'O', Out(Bits(1)), 'COUT', Out(Bit)] + \
ClockInterface(False, False)
testcircuit = DefineCircuit('test_add_cout_one', *args)
add = DefineAdd(1, cout=True)()
wire(testcircuit.I0, add.I0)
wire(testcircuit.I1, add.I1)
wire(testcircuit.O, add.O)
wire(testcircuit.COUT, add.COUT)
EndCircuit()
sim = CoreIRSimulator(testcircuit, testcircuit.CLK)
def test_add():
width = 4
mask = 2**width - 1
Add = DefineAdd(width)
assert generate_function_test_vectors(Add, lambda x, y: (x + y) & mask) == \
generate_simulator_test_vectors(Add)
def test_add_cin_two():
compile("build/test_add_cin_two", DefineAdd(4, cin=True), output="coreir")
assert check_files_equal(__file__, "build/test_add_cin_two.json",
"gold/test_add_cin_two.json")
def definition(TSBankGenerator):
flat_idx_width = getRAMAddrWidth(no * ni)
# next element each time_per_element clock
if time_per_element > 1:
index_in_cur_element = SizedCounterModM(time_per_element,
has_ce=has_ce,
has_reset=has_reset)
next_element = Decode(time_per_element - 1,
index_in_cur_element.O.N)(
index_in_cur_element.O)
else:
next_element = DefineCoreirConst(1, 1)()
# each element of the SSeq is a separate vector lane
first_lane_flat_idx = SizedCounterModM((no + io) * ni,
incr=ni,
has_ce=True,
has_reset=has_reset)()
time_counter = SizedCounterModM(no + io,
has_ce=True,
has_reset=has_reset)
wire(next_element.O, first_lane_flat_idx.CE)
wire(next_element.O, time_counter.CE)
if has_ce:
wire(TSBankGenerator.CE, index_in_cur_element.CE)
if has_reset:
wire(TSBankGenerator.RESET, index_in_cur_element.RESET)
wire(TSBankGenerator.RESET, first_lane_flat_idx.RESET)
wire(TSBankGenerator.RESET, time_counter.RESET)
lane_flat_idxs = [first_lane_flat_idx.O]
# compute the current flat_idx for each lane
for i in range(1, ni):
cur_lane_flat_idx_adder = DefineAdd(flat_idx_width)()
wire(cur_lane_flat_idx_adder.I0, first_lane_flat_idx.O)
wire(cur_lane_flat_idx_adder.I1,
DefineCoreirConst(flat_idx_width, i * no)().O)
lane_flat_idxs += [cur_lane_flat_idx_adder.O]
lane_flat_div_lcms = []
# conmpute flat_idx / lcm_dim for each lane
for i in range(ni):
cur_lane_lcm_div = DefineUDiv(flat_idx_width)()
wire(cur_lane_lcm_div.I0, lane_flat_idxs[0].O)
wire(cur_lane_lcm_div.I1,
DefineCoreirConst(lcm(no, ni), flat_idx_width)().O)
lane_flat_div_lcms += [cur_lane_flat_idx_adder.O]
# compute ((flat_idx % sseq_dim) + (flat_idx / lcm_dim)) % sseq_dim for each lane
# note that s_ts == flat_idx % sseq_dim
# only need to mod sseq_dim at end as that is same as also doing it flat_idx before addition
for i in range(ni):
pre_mod_add = DefineAdd(flat_idx_width)()
wire(pre_mod_add.I0, lane_flat_idxs[i])
wire(pre_mod_add.I1, lane_flat_div_lcms[i])
bank_mod = DefineUMod(flat_idx_width)()
wire(bank_mod.I0, pre_mod_add.O)
wire(bank_mod.I0, DefineCoreirConst(flat_idx_width, ni)().O)
wire(TSBankGenerator.bank[i],
bank_mod.O[0:TSBankGenerator.bank_width])
# compute t for each lane addr
for i in range(0, ni):
wire(TSBankGenerator.addr[i],
time_counter.O[0:TSBankGenerator.addr_width])
def definition(STBankGenerator):
flat_idx_width = getRAMAddrWidth(no * ni)
# next element each time_per_element clock
if time_per_element > 1:
index_in_cur_element = SizedCounterModM(time_per_element,
has_ce=has_ce,
has_reset=has_reset)
next_element = Decode(time_per_element - 1,
index_in_cur_element.O.N)(
index_in_cur_element.O)
else:
next_element = DefineCoreirConst(1, 1)()
# each element of the SSeq is a separate vector lane
first_lane_flat_idx = DefineCounterModM(ni + ii,
flat_idx_width,
cout=False,
has_ce=True,
has_reset=has_reset)()
wire(next_element.O[0], first_lane_flat_idx.CE)
if has_ce:
wire(STBankGenerator.CE, index_in_cur_element.CE)
if has_reset:
wire(STBankGenerator.RESET, index_in_cur_element.RESET)
wire(STBankGenerator.RESET, first_lane_flat_idx.RESET)
lane_flat_idxs = [first_lane_flat_idx.O]
# compute the current flat_idx for each lane
for i in range(1, no):
cur_lane_flat_idx_adder = DefineAdd(flat_idx_width)()
wire(cur_lane_flat_idx_adder.I0, first_lane_flat_idx.O)
wire(cur_lane_flat_idx_adder.I1,
DefineCoreirConst(flat_idx_width, i * ni)().O)
lane_flat_idxs += [cur_lane_flat_idx_adder.O]
lane_flat_div_lcms = []
lcm_dim = DefineCoreirConst(flat_idx_width, lcm(no, ni))()
# conmpute flat_idx / lcm_dim for each lane
for i in range(no):
cur_lane_lcm_div = DefineUDiv(flat_idx_width)()
wire(cur_lane_lcm_div.I0, lane_flat_idxs[i])
wire(cur_lane_lcm_div.I1, lcm_dim.O)
lane_flat_div_lcms += [cur_lane_lcm_div.O]
# compute ((flat_idx % sseq_dim) + (flat_idx / lcm_dim)) % sseq_dim for each lane
# only need to mod sseq_dim at end as that is same as also doing it flat_idx before addition
for i in range(no):
pre_mod_add = DefineAdd(flat_idx_width)()
wire(pre_mod_add.I0, lane_flat_idxs[i])
wire(pre_mod_add.I1, lane_flat_div_lcms[i])
bank_mod = DefineUMod(flat_idx_width)()
wire(bank_mod.I0, pre_mod_add.O)
wire(bank_mod.I1, DefineCoreirConst(flat_idx_width, no)().O)
wire(STBankGenerator.bank[i],
bank_mod.O[0:STBankGenerator.bank_width])
if len(bank_mod.O) > STBankGenerator.bank_width:
bits_to_term = len(bank_mod.O) - STBankGenerator.bank_width
term = TermAnyType(Array[bits_to_term, Bit])
wire(bank_mod.O[STBankGenerator.bank_width:], term.I)
# compute flat_idx / sseq_dim for each lane addr
for i in range(no):
flat_idx_sseq_dim_div = DefineUDiv(flat_idx_width)()
wire(flat_idx_sseq_dim_div.I0, lane_flat_idxs[0])
wire(flat_idx_sseq_dim_div.I1,
DefineCoreirConst(flat_idx_width, no)().O)
wire(STBankGenerator.addr[i],
flat_idx_sseq_dim_div.O[0:STBankGenerator.addr_width])
if len(flat_idx_sseq_dim_div.O) > STBankGenerator.addr_width:
bits_to_term = len(bank_mod.O) - STBankGenerator.addr_width
term = TermAnyType(Array[bits_to_term, Bit])
wire(flat_idx_sseq_dim_div.O[STBankGenerator.addr_width:],
term.I)
def test_add():
width = 4
mask = 2**width - 1
Add = DefineAdd(width)
assert function_test(Add, lambda x, y:
(x + y) & mask) == simulator_test(Add)