# Reduce interface
inType2 = m.In(m.Array(a * b, TIN))
outType2 = TOUT
# Top level module: line buffer input, reduce output
args = ['I', inType, 'O', outType2, 'WE', m.BitIn, 'V', m.Out(m.Bit)] + \
m.ClockInterface(False, False)
dscale = m.DefineCircuit('Downscale', *args)
# Line buffer declaration
lb = Linebuffer(cirb, inType, outType, imgType, True)
m.wire(lb.I, dscale.I)
m.wire(lb.wen, dscale.WE)
# Reduce declaration
red = ReduceParallel(cirb, samples, renameCircuitForReduce(DeclareAdd(width)))
# additive identity
coreirConst = DefineCoreirConst(width, 0)()
# select 16 samples to keep
k = 0
for i in [0, 3, 5, 8]:
for j in [0, 3, 7, 10]:
m.wire(red.I.data[k], lb.out[i][j])
k += 1
m.wire(red.I.identity, coreirConst.O)
m.wire(dscale.O, red.out)
m.wire(dscale.V, lb.valid)
m.EndCircuit()
inType2 = m.In(m.Array(4, TIN))
outType2 = m.Out(m.Array(16, Bit))
# Test circuit has line buffer's input and reduce's output
args = ['I', inType, 'O', outType2, 'WE', BitIn, 'V', m.Out(m.Bit),
'L00', TOUT, 'L01', TOUT, 'L10', TOUT, 'L11', TOUT] + \
m.ClockInterface(False, False)
testcircuit = m.DefineCircuit('STEN', *args)
# Line buffer declaration
lb = Linebuffer(cirb, inType, outType, imgType, True)
m.wire(lb.I, testcircuit.I)
m.wire(lb.wen, testcircuit.WE)
# # Reduce declaration
reducePar = ReduceParallel(cirb, 4, renameCircuitForReduce(DeclareAdd(16)))
coreirConst = DefineCoreirConst(16, 0)()
m.wire(reducePar.I.data[0], lb.out[0][0])
m.wire(reducePar.I.data[1], lb.out[0][1])
m.wire(reducePar.I.data[2], lb.out[1][0])
m.wire(reducePar.I.data[3], lb.out[1][1])
m.wire(reducePar.I.identity, coreirConst.O)
m.wire(testcircuit.O, reducePar.out)
m.wire(testcircuit.V, lb.valid)
m.wire(lb.out[0][0], testcircuit.L00)
m.wire(lb.out[0][1], testcircuit.L01)
m.wire(lb.out[1][0], testcircuit.L10)
m.wire(lb.out[1][1], testcircuit.L11)
width = 16
TIN = m.Array(width, m.BitIn)
TOUT = m.Array(width, m.Out(m.Bit))
# interface
inType = m.In(m.Array(a, TIN))
outType = TOUT
# test circuit has line buffer's input and reduce's output
args = ['I', inType, 'O', outType, 'WE', m.BitIn, 'V', m.Out(m.Bit)] + \
m.ClockInterface(False, False)
reduceHybrid = m.DefineCircuit('ReduceHybrid', *args)
# reduce Parallel
reducePar = ReduceParallel(cirb, a, renameCircuitForReduce(DeclareAdd(width)))
coreirConst = DefineCoreirConst(width, 0)()
# reduce sequential
reduceSeq = ReduceSequential(cirb, b, renameCircuitForReduce(DefineAdd(width)))
# top level input fed to reduce parallel input
m.wire(reduceHybrid.I, reducePar.I.data)
m.wire(reducePar.I.identity, coreirConst.out)
# reduce parallel output fed to reduce sequential input
m.wire(reducePar.out, reduceSeq.I)
# output of reduce sequential fed to top level output
m.wire(reduceSeq.out, reduceHybrid.O)
m.wire(reduceSeq.valid, reduceHybrid.V)
# Reduce interface
inType2 = In(Array(m * n, TIN))
outType2 = TOUT
# Top level module: line buffer input, reduce output
args = ['I', inType, 'O', outType2, 'WE', BitIn, 'V',
Out(Bit)] + ClockInterface(False, False)
top = DefineCircuit('Downscale', *args)
# Line buffer declaration
lb = Linebuffer(cirb, inType, outType, imgType, True)
wire(lb.I, top.I)
wire(lb.wen, top.WE)
# Reduce declaration
red = ReduceParallel(cirb, m * n, renameCircuitForReduce(DeclareAdd(b)))
# additive identity
coreirConst = DefineCoreirConst(b, 0)()
# flatten linebuffer output and wire to reduce parallel input
for i in range(n):
for j in range(m):
k = m * i + j
wire(red.I.data[k], lb.out[i][j])
wire(red.I.identity, coreirConst.out)
wire(top.O, red.out)
wire(top.V, lb.valid)
EndCircuit()
import magma as m
from magma.clock import *
from magma.backend.coreir_ import CoreIRBackend
from magma.bitutils import *
from coreir.context import *
from magma.simulator.coreir_simulator import CoreIRSimulator
import coreir
from magma.scope import Scope
from mantle.coreir import DefineCoreirConst
from mantle import CounterModM, Decode, SIPO
from magma.frontend.coreir_ import GetCoreIRModule
from mantle.coreir.arith import *
from mantle.primitives import DeclareAdd
c = coreir.Context()
cirb = CoreIRBackend(c)
scope = Scope()
width = 16
addID = DefineCoreirConst(width, 0)()
rpp = ReducePartiallyParallel(cirb, 8, 2,
renameCircuitForReduce(DeclareAdd(width)))
m.wire(addID.out, rpp.C)
m.EndCircuit()
module = GetCoreIRModule(cirb, rpp)
module.save_to_file("reducehybrid.json")