def test_ram(): main = m.DefineCircuit("main", "rdata", m.Out(m.Bit), "CLKIN", m.In(m.Clock)) ram = mantle.RAM(4, 1, name="ram") waddr = mantle.Counter(2, cout=False) wdata = mantle.Counter(1, cout=False) we = 1 raddr = mantle.Counter(2, cout=False) ram(raddr, waddr, wdata, we, CLK=main.CLKIN) m.wire(ram.RDATA[0], main.rdata) m.EndDefine() if m.mantle_target == "coreir": output = "coreir" suffix = "json" else: output = "verilog" suffix = "v" m.compile(f"build/test_common_ram_{m.mantle_target}", main, output) assert check_files_equal( __file__, f"build/test_common_ram_{m.mantle_target}.{suffix}", f"gold/test_common_ram_{m.mantle_target}.{suffix}")
def test_ram(): main = m.DefineCircuit("main", "rdata", m.Out(m.Bit), "CLKIN", m.In(m.Clock)) ram = mantle.RAM(4, 1) waddr = mantle.Counter(4) wdata = mantle.Counter(1) we = 1 raddr = mantle.FF()(mantle.Counter(4)) ram(raddr, waddr, wdata, we, CLK=main.CLKIN) m.wire(ram.RDATA, main.rdata) m.EndDefine() m.compile("build/test_common_ram", main)
def definition(io): edge_r = rising(io.SCK) edge_f = falling(io.SCK) # pixels come 16 bits (high and low byte) at a time bit_counter = mantle.Counter(4, has_ce=True, has_reset=True) m.wire(edge_r, bit_counter.CE) # find when the high and low byte are valid low = mantle.Decode(15, 4)(bit_counter.O) high = mantle.Decode(7, 4)(bit_counter.O) # shift registers to store high and low byte low_byte = mantle.PIPO(8, has_ce=True) high_byte = mantle.PIPO(8, has_ce=True) low_byte(0, io.DATA, low) high_byte(0, io.DATA, high) m.wire(low, low_byte.CE) m.wire(high, high_byte.CE) # assemble the 16-bit RGB565 value px_bits = (m.uint(mantle.LSL(16)((m.uint(m.concat(high_byte.O, zeros))), m.bits(8, 4))) + m.uint(m.concat(low_byte.O, zeros))) # extract the values for each color r_val = m.uint(mantle.LSR(16)((px_bits & RMASK), m.bits(11, 4))) g_val = m.uint(mantle.LSR(16)((px_bits & GMASK), m.bits(5, 4))) b_val = m.uint(px_bits & BMASK) # sum them to get grayscale (0 to 125) px_val = (r_val + g_val + b_val) # --------------------------UART OUTPUT---------------------------- # # run 16-bit UART at 2x speed baud = edge_r | edge_f # reset at start of pixel transfer ff1 = mantle.FF(has_ce=True) m.wire(baud, ff1.CE) u_reset = mantle.LUT2(I0 & ~I1)(io.VALID, ff1(io.VALID)) m.wire(u_reset, bit_counter.RESET) # generate load signal ff2 = mantle.FF(has_ce=True) m.wire(baud, ff2.CE) load = mantle.LUT3(I0 & I1 & ~I2)(io.VALID, high, ff2(high)) uart = UART(16) uart(CLK=io.CLK, BAUD=baud, DATA=px_val, LOAD=load) m.wire(px_val, io.PXV) m.wire(uart, io.UART) m.wire(load, io.LOAD)
def test_ram(): main = m.DefineCircuit("main", "rdata", m.Out(m.Bit), "CLKIN", m.In(m.Clock)) ram = mantle.RAM(4, 1) waddr = mantle.Counter(4, cout=False) wdata = mantle.Counter(1, cout=False) we = 1 raddr = mantle.Counter(4, cout=False) ram(raddr, waddr, wdata, we, CLK=main.CLKIN) m.wire(ram.RDATA[0], main.rdata) m.EndDefine() if m.mantle_target == "coreir": output = "coreir" else: output = "verilog" m.compile("build/test_common_ram", main, output)
import magma as m import mantle from mantle.util.lfsr import DefineLFSR from loam.shields.megawing import MegaWing if m.mantle_target == 'spartan3': from loam.boards.papilioone import PapilioOne as Papilio elif m.mantle_target == 'spartan6': from loam.boards.papiliopro import PapilioPro as Papilio LFSR8 = DefineLFSR(8, has_ce=True) megawing = MegaWing(Papilio) megawing.Clock.on() megawing.LED.on(8) main = megawing.main() counter = mantle.Counter(22) lfsr = LFSR8() m.wire(lfsr(ce=counter.COUT), main.LED) m.EndCircuit()
hx8kboard.J2[9].output().on() hx8kboard.J2[10].output().on() hx8kboard.J2[11].output().on() hx8kboard.J2[12].output().on() hx8kboard.J2[16].output().on() hx8kboard.J2[17].output().on() # hx8kboard.J2[18].output().on() # hx8kboard.J2[19].output().on() hx8kboard.J2[8].input().on() main = hx8kboard.main() # Generate the SCLK signal (12 MHz/32 = 375 kHz) clk_counter = mantle.Counter(2) sclk = clk_counter.O[-1] # Initialize Modules # ArduCAM cam = ArduCAM() m.wire(main.CLKIN, cam.CLK) m.wire(sclk, cam.SCK) m.wire(main.J2_8, cam.MISO) # Pre-processing process = Process() m.wire(main.CLKIN, process.CLK) m.wire(sclk, process.SCK) m.wire(cam.DATA, process.DATA)
from loam.shields.megawing import MegaWing from bit1 import Bit1 N = 32 NI = 2 NO = 2 def prog(): from bit1.isa import clr, set, O0 clr(O0) set(O0, jump=0) megawing = MegaWing(PapilioPro) megawing.Clock.on() megawing.Joystick.on() megawing.LED.on(NO) main = megawing.main() if NO == 1: main.LED = m.bits([main.LED]) slow = mantle.Counter(16) select = debounce(main.SELECT, slow.COUT) step = falling(select) bit1 = Bit1(prog, N, NI, NO, has_ce=True) m.wire(bit1(m.bits([1, 1]), ce=step), main.LED)
hx8kboard.J2[9].output().on() hx8kboard.J2[10].output().on() hx8kboard.J2[11].output().on() # hx8kboard.J2[12].output().on() # hx8kboard.J2[16].output().on() # hx8kboard.J2[17].output().on() # hx8kboard.J2[18].output().on() # hx8kboard.J2[19].output().on() main = hx8kboard.main() # "test" data init = [m.uint(i, 16) for i in range(16)] printf = mantle.Counter(4, has_ce=True) rom = ROM16(4, init, printf.O) clk_counter = mantle.Counter(5) sclk = clk_counter.O[4] edge_r = rising(sclk) edge_f = falling(sclk) baud = edge_r | edge_f bit_counter = mantle.Counter(4, has_ce=True, has_reset=True) m.wire(edge_r, bit_counter.CE) high = mantle.Decode(7, 4)(bit_counter.O) ff2 = mantle.FF(has_ce=True)
import magma as m import mantle from loam.boards.zed import Zed zed = Zed() zed.Clock.on() zed.LED.on(1) main = zed.main() counter = mantle.Counter(32) m.wire( counter.O[24], main.LED )
def definition(cam): edge_f = falling(cam.SCK) edge_r = rising(cam.SCK) # ROM to store commands rom_index = mantle.Counter(4, has_ce=True) rom = ROM16(4, init, rom_index.O) # Message length is 16 bits, setup counter to generate done signal # after EOM done_counter = mantle.Counter(5, has_ce=True, has_reset=True) count = done_counter.O done = mantle.Decode(16, 5)(count) # State machine to generate run signal (enable) run = mantle.DFF(has_ce=True) run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0]) run_n(done, trigger, run) run(run_n) m.wire(edge_f, run.CE) # Reset the message length counter after done run_reset = mantle.LUT2(I0 | ~I1)(done, run) done_counter(CE=edge_r, RESET=run_reset) # State variables for high-level state machine ready = mantle.LUT2(~I0 & I1)(run, edge_f) start = mantle.ULE(4)(rom_index.O, m.uint(3, 4)) burst = mantle.UGE(4)(rom_index.O, m.uint(9, 4)) # Shift register to store 16-bit command|data to send mosi = mantle.PISO(16, has_ce=True) # SPI enable is negative of load-don't load and shift out data at the # same time enable = mantle.LUT3(I0 & ~I1 & ~I2)(trigger, run, burst) mosi(~burst, rom.O, enable) m.wire(edge_f, mosi.CE) # Shit register to read in 8-bit data miso = mantle.SIPO(8, has_ce=True) miso(cam.MISO) valid = mantle.LUT2(~I0 & I1)(enable, edge_r) m.wire(valid, miso.CE) # Capture done state variable cap_done = mantle.SRFF(has_ce=True) cap_done(mantle.EQ(8)(miso.O, m.bits(0x08, 8)), 0) m.wire(enable & edge_r, cap_done.CE) # Use state variables to determine what commands are sent (how) increment = mantle.LUT4(I0 & (I1 | I2) & ~I3)( ready, start, cap_done, burst) m.wire(increment, rom_index.CE) # wire outputs m.wire(enable, cam.EN) m.wire(mosi.O, cam.MOSI) m.wire(miso.O, cam.DATA) m.wire(burst, cam.VALID) # --------------------------UART OUTPUT---------------------------- # # run UART at 2x SPI rate to allow it to keep up baud = edge_r | edge_f # reset when SPI burst read (image transfer) begins ff = mantle.FF(has_ce=True) m.wire(edge_r, ff.CE) u_reset = mantle.LUT2(I0 & ~I1)(burst, ff(burst)) # UART data out every 8 bits u_counter = mantle.CounterModM(8, 3, has_ce=True, has_reset=True) u_counter(CE=edge_r, RESET=u_reset) load = burst & rising(u_counter.COUT) uart = UART(8) uart(CLK=cam.CLK, BAUD=baud, DATA=miso, LOAD=load) # wire output m.wire(uart, cam.UART) # generate signal for when transfer is done data_count = mantle.Counter(18, has_ce=True) tx_done = mantle.SRFF(has_ce=True) # transfer has size 153600 bytes, first 2 bytes are ignored tx_done(mantle.EQ(18)(data_count.O, m.bits(153602, 18)), 0) m.wire(load, tx_done.CE) m.wire(load, data_count.CE) # wire output m.wire(tx_done, cam.DONE)
from magma.bitutils import int2seq import mantle from loam.boards.icestick import IceStick from rom import ROM icestick = IceStick() icestick.Clock.on() icestick.TX.output().on() main = icestick.main() valid = 1 init = [m.array(int2seq(ord(c), 8)) for c in 'hello, world \r\n'] printf = mantle.Counter(4, has_ce=True) rom = ROM(4, init, printf.O) data = m.array([rom.O[7], rom.O[6], rom.O[5], rom.O[4], rom.O[3], rom.O[2], rom.O[1], rom.O[0], 0]) counter = mantle.CounterModM(103, 8) baud = counter.COUT count = mantle.Counter(4, has_ce=True, has_reset=True) decode = mantle.Decode(15, 4) done = decode(count.O) run = mantle.DFF(has_ce=True) run_n = mantle.LUT3([0,0,1,0, 1,0,1,0]) run_n(done, valid, run.O)
main = icestick.main() # img_list = [0, 0, 0, 0, 0, 15840, 32752, 16176, 816, 1008, 480, 0, 0, 0, 0, # 0] # 9, last col->first col img_list = [ 0, 0, 0, 0, 960, 2016, 1632, 1632, 2016, 960, 224, 224, 224, 224, 64, 0 ] # 9, first row->last row # img_list = [0, 0, 0, 896, 984, 3680, 7216, 6204, 14456, 14448, 8160, 3840, # 0, 0, 0, 0] # 0 # img_list = range(2, 18) num_data = [m.uint(img_list[i], 16) for i in range(16)] # decrease the frequency to avoid timing violation counter = mantle.Counter(4) sclk = counter.O[-1] rom_idx = mantle.Counter(4, has_ce=True) full = mantle.SRFF(has_ce=True) check = mantle.EQ(4)(rom_idx.O, m.bits(15, 4)) full(check, 0) m.wire(falling(sclk), full.CE) rom_ce = rising(sclk) & ~full.O m.wire(rom_ce, rom_idx.CE) rom = ROM16(4, num_data, rom_idx.O) pipeline = Pipeline() m.wire(sclk, pipeline.CLK)
def definition(io): load = io.LOAD baud = rising(io.SCK) | falling(io.SCK) valid_counter = mantle.CounterModM(buf_size, 12, has_ce=True) m.wire(load & baud, valid_counter.CE) valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)] # len = 32 valid = m.GND for i in valid_list: valid = valid | mantle.Decode(i, 12)(valid_counter.O) # register on input st_in = mantle.Register(width, has_ce=True) st_in(io.DATA) m.wire(load, st_in.CE) # --------------------------DOWNSCALING----------------------------- # # downscale the image from 352x288 to 32x32 Downscale = m.DeclareCircuit( 'Downscale', "I_0_0", m.In(m.Array(1, m.Array(1, m.Array(width, m.Bit)))), "WE", m.In(m.Bit), "CLK", m.In(m.Clock), "O", m.Out(m.Array(width, m.Bit)), "V", m.Out(m.Bit)) dscale = Downscale() m.wire(st_in.O, dscale.I_0_0[0][0]) m.wire(1, dscale.WE) m.wire(load, dscale.CLK) add16 = mantle.Add(width) # needed for Add16 definition # --------------------------FILL IMG RAM--------------------------- # # each valid output of dscale represents an entry of 32x32 binary image # accumulate each group of 32 entries into a 32-bit value representing a row col = mantle.CounterModM(32, 6, has_ce=True) col_ce = rising(valid) m.wire(col_ce, col.CE) # shift each bit in one at a time until we get an entire row px_bit = mantle.ULE(16)(dscale.O, m.uint(THRESH, 16)) & valid row_reg = mantle.SIPO(32, has_ce=True) row_reg(px_bit) m.wire(col_ce, row_reg.CE) # reverse the row bits since the image is flipped row = reverse(row_reg.O) rowaddr = mantle.Counter(6, has_ce=True) img_full = mantle.SRFF(has_ce=True) img_full(mantle.EQ(6)(rowaddr.O, m.bits(32, 6)), 0) m.wire(falling(col.COUT), img_full.CE) row_ce = rising(col.COUT) & ~img_full.O m.wire(row_ce, rowaddr.CE) waddr = rowaddr.O[:5] rdy = col.COUT & ~img_full.O pulse_count = mantle.Counter(2, has_ce=True) we = mantle.UGE(2)(pulse_count.O, m.uint(1, 2)) pulse_count(CE=(we|rdy)) # ---------------------------UART OUTPUT----------------------------- # row_load = row_ce row_baud = mantle.FF()(baud) uart_row = UART(32) uart_row(CLK=io.CLK, BAUD=row_baud, DATA=row, LOAD=row_load) uart_addr = UART(5) uart_addr(CLK=io.CLK, BAUD=row_baud, DATA=waddr, LOAD=row_load) m.wire(waddr, io.WADDR) m.wire(img_full, io.DONE) #img_full m.wire(uart_row, io.UART) #uart_st m.wire(row, io.O) m.wire(we, io.VALID) m.wire(valid, io.T0) m.wire(uart_addr, io.T1)
def definition(cls): counter = mantle.Counter(width, has_ce=has_en) m.wire(counter.O, cls.out) m.wire(counter.CLK, cls.clk) if has_en: m.wire(counter.CE, cls.en)
from loam.boards.papiliopro import PapilioPro from loam.shields.megawing import MegaWing from bit1 import Bit1 N = 32 NR = 4 NI = NR NO = NR + 4 def prog(): from bit1.isa import not_, if1, jump for i in range(NR): not_(i, i) if1(i, 0) jump( 0 ) megawing = MegaWing(PapilioPro) megawing.Clock.on() megawing.LED.on(NO-NR) main = megawing.main() clock = mantle.Counter(22) bit1 = Bit1( prog, N, NI, NO, has_ce=True ) O = bit1( bit1.O[:NR], ce=clock.COUT ) m.wire( bit1.O[NR:], main.LED )
def definition(io): load = io.LOAD baud = rising(io.SCK) | falling(io.SCK) valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True) m.wire(load & baud, valid_counter.CE) valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)] valid = m.GND for i in valid_list: valid = valid | mantle.Decode(i, 13)(valid_counter.O) # register on input st_in = mantle.Register(16, has_ce=True) st_in(io.DATA) m.wire(load, st_in.CE) # --------------------------DOWNSCALING----------------------------- # # downscale the image from 320x240 to 16x16 Downscale = m.DeclareCircuit( 'Downscale', "I_0_0", m.In(m.Array(1, m.Array(1, m.Array(16, m.Bit)))), "WE", m.In(m.Bit), "CLK", m.In(m.Clock), "O", m.Out(m.Array(16, m.Bit)), "V", m.Out(m.Bit)) dscale = Downscale() m.wire(st_in.O, dscale.I_0_0[0][0]) m.wire(1, dscale.WE) m.wire(load, dscale.CLK) add16 = mantle.Add(16) # needed for Add16 definition # --------------------------FILL IMG RAM--------------------------- # # each valid output of dscale represents a pixel in 16x16 binary image # accumulate each group of 16 pixels into a 16-bit value representing # a row in the image col = mantle.CounterModM(16, 5, has_ce=True) col_ce = rising(valid) m.wire(col_ce, col.CE) # shift each bit in one at a time until we get an entire row px_bit = mantle.ULE(16)(dscale.O, m.uint(THRESH, 16)) & valid row_reg = mantle.SIPO(16, has_ce=True) row_reg(px_bit) m.wire(col_ce, row_reg.CE) # reverse the row bits since the image is flipped row = reverse(row_reg.O) rowaddr = mantle.Counter(5, has_ce=True) img_full = mantle.SRFF(has_ce=True) img_full(mantle.EQ(5)(rowaddr.O, m.bits(16, 5)), 0) m.wire(falling(col.COUT), img_full.CE) row_ce = rising(col.COUT) & ~img_full.O m.wire(row_ce, rowaddr.CE) waddr = rowaddr.O[:4] # we_counter = mantle.CounterModM(16, 5, has_ce=True) # m.wire(rising(valid), we_counter.CE) rdy = col.COUT & ~img_full.O pulse_count = mantle.Counter(5, has_ce=True) we = mantle.UGE(5)(pulse_count.O, m.uint(1, 5)) pulse_count(CE=(we | rdy)) # ---------------------------UART OUTPUT----------------------------- # row_load = row_ce row_baud = mantle.FF()(baud) uart_row = UART(16) uart_row(CLK=io.CLK, BAUD=row_baud, DATA=row, LOAD=row_load) uart_addr = UART(4) uart_addr(CLK=io.CLK, BAUD=row_baud, DATA=waddr, LOAD=row_load) # split 16-bit row data into 8-bit packets so it can be parsed low_byte = row & LOW_MASK high_byte = row & HIGH_MASK uart_counter = mantle.CounterModM(8, 4, has_ce=True) m.wire(rising(valid), uart_counter.CE) m.wire(waddr, io.WADDR) m.wire(img_full, io.DONE) m.wire(uart_row, io.UART) m.wire(row, io.O) m.wire(we, io.VALID)
''' img_list = [ 0, 0, 0, 0, 960, 4064, 48, 32, 96, 192, 192, 384, 768, 512, 1536, 0 ] # from arducam #img_list = [0, 0, 0, 0, 64, 57440, 50720, 50976, 50592, 64576, 28672, 0, 0, 0, 0, 32768] # 3, last col->first col #img_list = [0, 0, 192, 480, 816, 528, 528, 528, 528, 1552, 1552, 560, 880, 992, 448, 0] # 0 # [1536, 3840, 8064, 6528, 4224, 4224, 6400, 3840, 3840, 8064, 14720, 14720, 14784, 14784, 16256, 7936] # [0, 1, 256, 1920, 3136, 2112, 64, 128, 128, 256, 768, 1536, 4080, 8176, 6144, 0] num_data = [m.uint(img_list[i], 16) for i in range(16)] # decrease the frequency to avoid timing violation counter = mantle.Counter(5) sclk = counter.O[4] baud = mantle.FF()(rising(sclk) | falling(sclk)) rom_idx = mantle.Counter(5, has_ce=True) addr = rom_idx.O[:4] bit_counter = mantle.Counter(5, has_ce=True) m.wire(rising(sclk), bit_counter.CE) we = mantle.Decode(0, 5)(bit_counter.O) load = rising(we) full = mantle.SRFF(has_ce=True) check = mantle.EQ(5)(rom_idx.O, m.bits(16, 5)) full(check, 0)
import magma as m import mantle from loam.boards.mojo import Mojo mojo = Mojo() mojo.Clock.on() mojo.LED1.on() main = mojo.main() N = 32 counter = mantle.Counter( N ) count, cout = counter() m.wire( count[24], main.LED1 )
NI = 1 NO = 8 def prog(): from bit1.isa import set, clr, halt for i in range(NO): j = (i - 1 + NO) % NO set(i) clr(j) clr(NO - 1) halt() megawing = MegaWing(PapilioPro) megawing.Clock.on() megawing.Joystick.on() megawing.LED.on(NO) main = megawing.main() slow = mantle.Counter(16) select = debounce(main.SELECT, slow.COUT) step = falling(select) clock = mantle.Counter(24) bit1 = Bit1(prog, N, NI, NO, has_ce=True, has_reset=True) m.wire(bit1(m.bits(0, 1), ce=clock.COUT, reset=step), main.LED)
# size of buffer for storing image n rows at a time buf_size = wi * b - 1 # 4800 - 1 = 4799 hx8kboard = HX8KBoard() hx8kboard.Clock.on() hx8kboard.J2[9].output().on() hx8kboard.J2[10].output().on() hx8kboard.J2[11].output().on() hx8kboard.J2[12].output().on() main = hx8kboard.main() # "test" data init = [m.uint(i, 16) for i in range(16)] printf = mantle.Counter(4, has_ce=True) rom = ROM16(4, init, printf.O) # baud for uart output clock = mantle.CounterModM(103, 8) baud = clock.COUT bit_counter = mantle.Counter(5, has_ce=True) m.wire(baud, bit_counter.CE) load = mantle.Decode(0, 5)(bit_counter.O) valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True) m.wire(load & baud, valid_counter.CE) valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)] # len = 16
def definition(io): load = io.LOAD baud = io.BAUD valid_counter = mantle.CounterModM(buf_size, 13, has_ce=True) m.wire(load & baud, valid_counter.CE) valid_list = [wi * (b - 1) + i * a - 1 for i in range(1, wo + 1)] valid = m.GND for i in valid_list: valid = valid | mantle.Decode(i, 13)(valid_counter.O) # register on input st_in = mantle.Register(16, has_ce=True) st_in(io.DATA) m.wire(load, st_in.CE) # --------------------------DOWNSCALING----------------------------- # # downscale the image from 320x240 to 16x16 Downscale = m.DeclareCircuit( 'Downscale', "I_0_0", m.In(m.Array(1, m.Array(1, m.Array(16, m.Bit)))), "WE", m.In(m.Bit), "CLK", m.In(m.Clock), "O", m.Out(m.Array(16, m.Bit)), "V", m.Out(m.Bit)) dscale = Downscale() m.wire(st_in.O, dscale.I_0_0[0][0]) m.wire(1, dscale.WE) m.wire(load, dscale.CLK) add16 = mantle.Add(16) # needed for Add16 definition # --------------------------FILL IMG RAM--------------------------- # # each valid output of dscale represents an entry of 16x16 binary image # accumulate each group of 16 entries into a 16-bit value representing # a row of the image col = mantle.Counter(4, has_ce=True) row_full = mantle.SRFF(has_ce=True) row_full(mantle.EQ(4)(col.O, m.bits(15, 4)), 0) m.wire(falling(dscale.V), row_full.CE) col_ce = rising(dscale.V) & ~row_full.O m.wire(col_ce, col.CE) row = mantle.Counter(4, has_ce=True) img_full = mantle.SRFF(has_ce=True) img_full(mantle.EQ(4)(row.O, m.bits(15, 4)), 0) m.wire(falling(col.COUT), img_full.CE) row_ce = rising(col.COUT) & ~img_full.O m.wire(row_ce, row.CE) # ---------------------------UART OUTPUT----------------------------- # uart_st = UART(16) uart_st(CLK=io.CLK, BAUD=baud, DATA=dscale.O, LOAD=load) m.wire(row.O, io.ROW) m.wire(img_full.O, io.DONE) m.wire(uart_st.O, io.UART)
width = 16 TIN = m.Array(width, m.BitIn) TOUT = m.Array(width, m.Out(m.Bit)) icestick = IceStick() icestick.Clock.on() for i in range(3): icestick.J3[i].output().on() main = icestick.main() # baud for uart output clock = mantle.CounterModM(103, 8) baud = clock.COUT bit_counter = mantle.Counter(5, has_ce=True) m.wire(baud, bit_counter.CE) load = mantle.Decode(0, 5)(bit_counter.O) # # "test" data # init = [m.uint(i, 16) for i in range(16)] # printf = mantle.Counter(4, has_ce=True) # rom = ROM16(4, init, printf.O) # m.wire(load & baud, printf.CE) #---------------------------STENCILING-----------------------------# ReduceHybrid = m.DeclareCircuit('ReduceHybrid', 'I_0', m.In(m.Array(a, TIN)), 'I_1', m.In(m.Array(a, TIN)), 'O', TOUT, 'WE', m.BitIn, 'V', m.Out(m.Bit), 'CLK',
#out( 1,0, 0) #inst([0,0, 0]) #inst([1,1, 0]) #inst([0,0, 0]) #inst([1,1, 0], ZERO, label()-1 ) #out( 1,0, 1, jump=label()) # halt papilio = PapilioPro() papilio.Clock.on() for i in range(3): papilio.A[i].output().on() main = papilio.main() clock = mantle.Counter(6)() reset = clock.COUT counter = mantle.Counter(5, has_ce=True) mosi = mantle.PISO(16, has_ce=True) bit1 = Bit1(main, N, NI, NO, mode='parallel', has_reset=True)) sclk, ss = bit1(counter.O[4], reset=reset) counter(ce=sclk) mosi( 0, m.bits(1,16), reset, ce=reset|sclk ) m.wire( ss, main.A[0] ) m.wire( sclk, main.A[1] ) m.wire( mosi.O, main.A[2] )