def __init__(self, width, num_tracks, core_inputs):
super().__init__()
self.width = width
self.num_tracks = num_tracks
assert core_inputs == 1
self.core_inputs = core_inputs
MuxCls = mantle.DefineMux(self.num_tracks, self.width)
self.muxs = [FromMagma(MuxCls) for _ in range(self.num_tracks)]
T = magma.Array(self.num_tracks, magma.Bits(self.width))
bits_per_sel = math.ceil(math.log(self.num_tracks, 2))
self.add_ports(
I=magma.In(T),
core_in=magma.In(magma.Array(self.core_inputs, T.T)),
O=magma.Out(T),
)
for i in range(self.num_tracks):
self.add_config(f"sel_{i}", bits_per_sel)
self.selects = [getattr(self, f"sel_{i}") \
for i in range(self.num_tracks)]
for i in range(self.num_tracks):
mux = self.muxs[i]
for j in range(self.num_tracks):
mux_in = self.I[j] if i != j else self.core_in[0]
self.wire(mux_in, getattr(mux, f"I{j}"))
self.wire(self.selects[i], mux.S)
self.wire(mux.O, self.O[i])
def __init__(self, height, width):
super().__init__()
self.height = height
self.width = width
T = magma.Bits(self.width)
# In the case that @height <= 1, we make this circuit a simple
# pass-through circuit.
if self.height <= 1:
self.add_ports(
I=magma.In(magma.Array(1, T)),
O=magma.Out(T),
)
self.wire(self.ports.I[0], self.ports.O)
self.sel_bits = 0
return
MuxCls = mantle.DefineMux(self.height, self.width)
self.mux = FromMagma(MuxCls)
self.sel_bits = magma.bitutils.clog2(self.height)
self.add_ports(
I=magma.In(magma.Array(self.height, T)),
S=magma.In(magma.Bits(self.sel_bits)),
O=magma.Out(T),
)
for i in range(self.height):
self.wire(self.ports.I[i], self.mux.ports[f"I{i}"])
mux_in = self.ports.S if self.sel_bits > 1 else self.ports.S[0]
self.wire(mux_in, self.mux.ports.S)
self.wire(self.mux.ports.O, self.ports.O)
def definition(io):
if height <= 1:
magma.wire(io.I[0], io.O)
else:
mux = mantle.DefineMux(height, width)()
for i in range(height):
magma.wire(io.I[i], mux.interface.ports[f"I{i}"])
mux_in = io.S if sel_bits > 1 else io.S[0]
magma.wire(mux_in, mux.S)
magma.wire(mux.O, io.O)
def __init__(self, height, width):
super().__init__()
self.height = height
self.width = width
MuxCls = mantle.DefineMux(self.height, self.width)
self.mux = FromMagma(MuxCls)
T = magma.Bits(width)
sel_bits = magma.bitutils.clog2(self.height)
self.add_ports(
I=magma.In(magma.Array(self.height, T)),
S=magma.In(magma.Bits(sel_bits)),
O=magma.Out(T),
)
for i in range(self.height):
self.wire(self.I[i], getattr(self.mux, f"I{i}"))
self.wire(self.S, self.mux.S)
self.wire(self.mux.O, self.O)
def __init__(self, width, num_tracks):
super().__init__()
self.width = width
self.num_tracks = num_tracks
is_power_of_two = lambda x: x != 0 and ((x & (x - 1)) == 0)
assert is_power_of_two(self.num_tracks)
self.mux = FromMagma(mantle.DefineMux(self.num_tracks, self.width))
T = magma.Bits(self.width)
sel_bits = math.ceil(math.log(self.num_tracks, 2))
self.add_ports(
I=magma.In(magma.Array(self.num_tracks, T)),
O=magma.Out(T),
)
self.add_configs(sel=sel_bits, )
for i in range(self.num_tracks):
self.wire(self.I[i], getattr(self.mux, f"I{i}"))
self.wire(self.sel, self.mux.S)
self.wire(self.mux.O, self.O)
def definition(circuit):
MuxT = mantle.DefineMux(2, T=type(circuit.I0))
circuit.O @= MuxT()(circuit.I0, circuit.I1, circuit.S)
def test_mux(height, width):
Test = mantle.DefineMux(height, width)
#sim( Test, None )
com(Test, f'mux{height}x{width}')
def test_mux(height, width):
Test = mantle.DefineMux(height, width)
sim(Test, lambda i0, i1, s: i1 if s else i0)
com(Test, f'mux{height}x{width}')
def test_mux(width):
Test = mantle.DefineMux(2,width)
com(f'Mux2x{width}', binary(Test, width) )
