class Counter(Circuit):
name = name_
io = IO(**dict(zip(args[::2], args[1::2])))
add = DefineAdd(n, cin=cin, cout=cout)()
mux = Mux(2, n)
reg = Register(n, has_ce=has_ce, has_reset=has_reset)
wire(reg.O, add.I0)
wire(array(incr, n), add.I1)
wire(add.O, mux.I0)
wire(io.DATA, mux.I1)
wire(io.LOAD, mux.S)
reg(mux.O)
next = False
if next:
wire(mux.O, io.O)
else:
wire(reg.O, io.O)
if cin:
wire(io.CIN, add.CIN)
if cout:
wire(add.COUT, io.COUT) # this is fishy because of the LOAD
def definition(upsampleSequential):
dehydrate = Dehydrate(cirb, T)
hydrate = Hydrate(cirb, T)
valueStoreReg = Register(dehydrate.size,
has_ce=has_ce,
has_reset=has_reset)
mux = Mux(width=dehydrate.size)
counter = SizedCounterModM(n, has_ce=has_ce or has_reset)
eq0 = Decode(0, counter.O.N)(counter.O)
wire(upsampleSequential.I, dehydrate.I)
wire(dehydrate.out, valueStoreReg.I)
# on first clock cycle, send the input directly out. otherwise, use the register
wire(eq0, mux.S)
wire(valueStoreReg.O, mux.I0)
wire(upsampleSequential.I, mux.I1)
wire(mux.O, hydrate.I)
wire(hydrate.out, upsampleSequential.O)
wire(eq0, upsampleSequential.READY)
# reset counter on clock enable or reset, setup both reset and CE for reg
if has_ce and has_reset:
wire(counter.CE,
And(2)(upsampleSequential.RESET, upsampleSequential.CE))
if has_ce:
wire(valueStoreReg.CE, upsampleSequential.CE)
if not has_reset:
wire(counter.CE, upsampleSequential.CE)
if has_reset:
wire(valueStoreReg.RESET, upsampleSequential.RESET)
if not has_ce:
wire(counter.RESET, upsampleSequential.RESET)
def Sequencer(n):
addr = Bus(n)
incr = Wire()
jump = Wire()
push = Wire()
pop = Wire()
we = Wire()
#
# o=True makes the combinational output be the output of the counter
# (rather than the register).
#
print 'building sp'
newsp = UpDownCounter(4, o=True)(push, pop, ce=we)
print 'building pc'
PC = RAM(n)
print 'building mux'
newpc = Mux(2, n)([PC, addr], jump)
print 'wiring pc'
PC(newpc, newsp, we, incr)
return Module([incr, jump, addr, push, pop], newpc, ce=we)
def definition(io):
# didn't work with coreir because the rst/bit conversion
# clkEn = io.push | io.pop | m.bit(io.rst)
########################## pointer logic ##############################
ptrreg = DefineRegister(PTRWID,
init=0,
has_ce=True,
has_reset=True,
_type=m.UInt)
wrPtr = ptrreg(name="wrPtr")
rdPtr = ptrreg(name="rdPtr")
# wire clocks
m.wireclock(io, wrPtr)
m.wireclock(io, rdPtr)
# wire resets
m.wire(wrPtr.RESET, io.rst)
m.wire(rdPtr.RESET, io.rst)
# wire enables
m.wire(wrPtr.CE, io.push)
m.wire(rdPtr.CE, io.pop)
# next values increment by one
m.wire(wrPtr.I, wrPtr.O + m.uint(1, PTRWID))
m.wire(rdPtr.I, rdPtr.O + m.uint(1, PTRWID))
######################### end pointer logic ###########################
######################### full and empty logic ########################
m.wire(io.empty, wrPtr.O == rdPtr.O)
m.wire(io.full, (wrPtr.O[1:PTRWID] == rdPtr.O[1:PTRWID]) &
(wrPtr.O[0] != rdPtr.O[0]))
######################### end full and empty logic ####################
########################### entry logic ###############################
# Create and write
entries = []
entryReg = DefineRegister(WIDTH,
init=0,
has_ce=True,
has_reset=False,
_type=m.Bits)
for i in range(DEPTH):
entry = entryReg(name="entry" + str(i))
m.wire(
entry.CE, io.push &
m.bit(m.uint(wrPtr.O[1:PTRWID]) == m.uint(i, PTRWID - 1)))
m.wire(entry.I, io.data_in)
entries.append(entry)
# Connect mux
outmux = Mux(DEPTH, WIDTH)
for i in range(DEPTH):
m.wire(getattr(outmux, "I" + str(i)), entries[i].O)
m.wire(rdPtr.O[1:PTRWID], outmux.S)
m.wire(outmux.O, io.data_out)
def definition(io):
Is = [io.I[i] for i in range(n)]
muxes = map_(Mux(2), n)
for i in range(n):
shifti = i - k
I = bits([Is[i], Is[shifti] if shifti >= 0 else io.SI])
muxes[i]( I, io.S )
for i in range(n):
Is[i] = muxes[i].O
wire(bits(Is), io.O)
def mux(I, S, **kwargs):
if isinstance(S, int):
return I[S]
elif S.const():
return I[seq2int(S.bits())]
T = type(I[0])
# Support using Bits(1) for select on 2 elements
if len(I) == 2 and isinstance(S, m.Array) and \
issubclass(S.T, m.Digital) and len(S) == 1:
S = S[0]
return Mux(len(I), T=T, **kwargs)(*I, S)
def DefineCounterLoad(n,
cin=False,
cout=True,
incr=1,
next=False,
has_ce=False,
has_reset=False):
name = _CounterName('CounterLoad', n, has_ce, has_reset)
args = []
args += ['DATA', In(UInt(n))]
args += ['LOAD', In(Bit)]
if cin:
args += ['CIN', In(Bit)]
args += ["O", Out(UInt(n))]
if cout:
args += ["COUT", Out(Bit)]
args += ClockInterface(has_ce, has_reset)
Counter = DefineCircuit(name, *args)
add = DefineAdd(n, cin=cin, cout=cout)()
mux = Mux(2, n)
reg = Register(n, has_ce=has_ce, has_reset=has_reset)
wire(reg.O, add.I0)
wire(array(incr, n), add.I1)
wire(add.O, mux.I0)
wire(Counter.DATA, mux.I1)
wire(Counter.LOAD, mux.S)
reg(mux.O)
if next:
wire(mux.O, Counter.O)
else:
wire(reg.O, Counter.O)
if cin:
wire(Counter.CIN, add.CIN)
if cout:
wire(add.COUT, Counter.COUT) # this is fishy because of the LOAD
wireclock(Counter, reg)
EndCircuit()
return Counter
def definition(io):
pc = Register(n, has_ce=True)
add = Add(n)
mux = Mux(2, n)
add( pc, bits(1,n=n) )
pc(mux)
wire(add.O, mux.I0)
wire(io.addr, mux.I1)
wire(io.jump, mux.S)
wire(io.CLK, pc.CLK)
wire(io.we, pc.CE)
wire(pc.O, io.O)
def dynamic_mux_select(self, S):
if isinstance(S, m.Type):
if isinstance(self.T, m._BitKind):
length = None
else:
length = len(self.T)
height = len(self)
inputs = self.ts[:]
if m.mantle_target == "ice40" and height not in [2, 4, 8, 16]:
if height > 16:
raise NotImplementedError()
orig_height = height
height = 2**m.bitutils.clog2(height)
if not isinstance(inputs[0], m._BitType):
raise NotImplementedError(type(inputs[0]))
inputs.extend([m.bit(0) for _ in range(height - orig_height)])
return Mux(height, length)(*inputs, S)
return orig_get_item(self, S)
def MUXs(n, width):
return [Mux(2, width) for i in range(n)]
def mux2(y):
return curry(Mux(2), prefix='I')
def mux(I, S):
if isinstance(S, int):
return I[S]
elif S.const():
return I[seq2int(S.bits())]
return Mux(len(I), get_length(I[0]))(*I, S)
def MUXs(n):
return [Mux(2, 8) for i in range(n)]
def definition(io):
invert = Invert(n)
mux = Mux(2, n)
m.wire(mux(io.I, invert(io.I), io.I[n - 1]), io.O)
