def __init__(self, plat):
neopixel_gpio = [('neopixel', 0, Subsignal('tx', Pins('PMOD:0')),
IOStandard('LVCMOS33'))]
plat.add_extension(neopixel_gpio)
neopixel_pads = plat.request('neopixel')
leds = plat.request('user_led')
serial_pads = plat.request('serial')
self.submodules.uart = UART(serial_pads,
baud_rate=115200,
clk_freq=12000000)
self.submodules.restrider = Restrider()
data = Signal(8)
self.submodules.uart_fsm = FSM()
self.uart_fsm.act(
'RX',
If(
self.uart.rx_ready,
self.uart.rx_ack.eq(1),
NextValue(data, self.uart.rx_data),
NextState('INGEST'),
))
self.comb += self.restrider.data_in.eq(data)
self.uart_fsm.act(
'INGEST',
self.restrider.latch_data.eq(1),
NextState('RX'),
)
N_PIXELS = 8
self.submodules.fifo = SyncFIFOBuffered(24, N_PIXELS)
pixel_data = Signal(24)
self.submodules.slurp_fsm = FSM()
self.slurp_fsm.act(
'IDLE', self.fifo.we.eq(0),
If(
self.restrider.done,
self.restrider.out_read_ack.eq(1),
NextValue(pixel_data, self.restrider.data_out),
NextState('CHUNK'),
))
self.comb += self.fifo.din.eq(pixel_data)
self.slurp_fsm.act(
'CHUNK',
If(
self.fifo.writable,
self.fifo.we.eq(1),
),
NextState('IDLE'),
)
self.submodules.neopixels = WS2812Controller(neopixel_pads, self.fifo,
12000000)
self.comb += self.neopixels.write_en.eq(self.fifo.level == N_PIXELS)
def __init__(self, plat):
from migen.build.generic_platform import Subsignal, IOStandard, Pins
neopixel_gpio = [
('neopixel', 0,
Subsignal('tx', Pins('PMOD:0')),
IOStandard('LVCMOS33')
)
]
plat.add_extension(neopixel_gpio)
neopixel_pads = plat.request('neopixel')
N_PIXELS = 8
fifo = SyncFIFO(24, N_PIXELS)
self.submodules.controller = WS2812Controller(neopixel_pads, fifo, 12000000)
def mk_extensions(self):
ext_list = None
if self.extensions:
ext_list = []
for name, ext_data in self.extensions.items():
if name not in ("serial", "user_led"):
print("extensions must be one of \"serial\" or \"user_led\"")
exit(2)
ext_count = 0
# Extensions can have more than one instance.
for inst in ext_data:
subsignals = []
pins = []
io_standard = []
pins_cfg = inst.get("pins")
subsig_cfg = inst.get("subsignals")
io_cfg = inst.get("io_standard")
if pins_cfg is not None and subsig_cfg is not None:
print("extensions must contain \"pins\" or \"subsignals\", but not both")
exit(3)
if pins_cfg:
pins.append(Pins(pins_cfg))
if subsig_cfg:
for sub_name, sub_data in subsig_cfg.items():
subsignals.append(Subsignal(sub_name, Pins(sub_data["pins"])))
# io_standard on subsignal not supported yet.
if io_cfg:
io_standard.append(IOStandard(io_cfg))
ext_list.append((name, ext_count, *pins, *subsignals, *io_standard))
ext_count = ext_count + 1
return ext_list
def main():
plat = icestick.Platform()
debugpins = [119, 118, 117, 116, 115, 114, 113, 112]
plat.add_extension([
('sio', 0,
Subsignal('rst', Pins('48')),
Subsignal('txd', Pins('56')),
Subsignal('rxd', Pins('60')),
Subsignal('sclk', Pins('61')),
Subsignal('busy', Pins('62')),
Subsignal('tclk', Pins('47')),
IOStandard('LVCMOS33'),
),
] + [
('debug', i, Pins(str(p)), IOStandard('LVCMOS33')) for i, p in enumerate(debugpins)
])
# Randomize seed because it doesn't get routed with the default of 1.
plat.toolchain.pnr_opt = "-q -r"
plat.build(Top(plat))
plat.create_programmer().flash(0, 'build/top.bin')
from litex.soc.cores.clock import iCE40PLL
from migen import *
from migen.build.generic_platform import Pins, Subsignal
from migen.build.platforms import icebreaker
from vga_timing import VgaTiming
from testpattern import TestPattern
vga_pmod = [
(
'vga',
0,
Subsignal('hsync', Pins('PMOD1B:4')),
Subsignal('vsync', Pins('PMOD1B:5')),
Subsignal('red',
Pins(' '.join('PMOD1A:{}'.format(x) for x in range(0, 4)))),
Subsignal('green', Pins(' '.join(f'PMOD1B:{x}' for x in range(0, 4)))),
Subsignal('blue', Pins(' '.join(f'PMOD1A:{x}' for x in range(4, 8)))),
),
]
class VgaTest(Module):
def __init__(self, vga, clk12):
self.clock_domains.sys = ClockDomain()
self.comb += self.sys.clk.eq(clk12)
self.clock_domains.vga = ClockDomain()
self.vga_clk_pll = iCE40PLL(primitive='SB_PLL40_PAD')
self.submodules.vga_clk_pll = self.vga_clk_pll
self.vga_clk_pll.register_clkin(self.sys.clk, 12e6)
def __init__(self, **kwargs):
super().__init__(**kwargs)
super().__getattribute__("add_extension")([
("ps", 0, Subsignal("clk", Pins("B24"), IOStandard("LVCMOS33")),
Subsignal("por_b", Pins("C23"), IOStandard("LVCMOS33")),
Subsignal("srst_b", Pins("A22"), IOStandard("LVCMOS18"))),
("ddr", 0,
Subsignal(
"dq",
Pins(
"J26 F25 J25 G26 H26 H23 J24 J23 K26 L23 M26 K23 M25 N24 M24 N23 "
"R26 P24 N26 P23 T24 T25 T23 R23 V24 U26 U24 U25 W26 Y25 Y26 W23"
), IOStandard("SSTL15_T_DCI")),
Subsignal("dm", Pins("G24 K25 P26 V26"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n", Pins("G25 L25 R25 W25"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("H24 L24 P25 W24"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal(
"a",
Pins(
"K22 K20 N21 L22 M20 N22 L20 J21 T20 U20 M22 H21 P20 J20 R20"
), IOStandard("SSTL15")),
Subsignal("ba", Pins("U22 T22 R22"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("Y23"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("V21"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("W21"), IOStandard("SSTL15_T_DCI")),
Subsignal("ras_n", Pins("V23"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("V22"), IOStandard("SSTL15")),
Subsignal("odt", Pins("Y22"), IOStandard("SSTL15")),
Subsignal("cke", Pins("U21"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("Y21"), IOStandard("SSTL15")),
Subsignal("clk_n", Pins("P21"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("R21"), IOStandard("DIFF_SSTL15")),
Subsignal("reset_n", Pins("H22"), IOStandard("SSTL15"))),
])
def __init__(self, **kwargs):
super().__init__(**kwargs)
self.add_extension([
(
"ps",
0,
Subsignal(
"clk", Pins("E7"), IOStandard("LVCMOS33")
), # "system clock" block on schematics is powered by 3.3V
Subsignal(
"por_b", Pins("C7"), IOStandard("LVCMOS25")
), # shared with Ethernet reset, and Ethernet is 2.5V on schematics
Subsignal("srst_b", Pins("B10"),
IOStandard("LVCMOS25"))), # pullup to 2.5V near TP3
# SDRAM is undocumented but these pins are fixed on Zynq.
("ddr", 0,
Subsignal("a",
Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")),
Subsignal("cke", Pins("N3"), IOStandard("SSTL15")),
Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15")),
Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15")),
Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")),
Subsignal("dm", Pins("A1 F1 T1 Y1"), IOStandard("SSTL15_T_DCI")),
Subsignal(
"dq",
Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1 "
"P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n", Pins("B2 F2 T2 W4"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("C2 G2 R2 W5"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15")),
Subsignal("odt", Pins("N5"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI")),
Subsignal("we_n", Pins("M5"), IOStandard("SSTL15"))),
])
plat = ice40_hx8k_b_evn.Platform()
# remove the -l option: auto-promote nets to globals
plat.toolchain.build_template[
1] = "arachne-pnr -r {pnr_pkg_opts} -p {build_name}.pcf {build_name}.blif -o {build_name}.txt"
plat.add_extension([
("debug", 0, Pins("P16 N16 M16 K15")),
("mclk", 0, Pins("R15")),
("wck", 0, Pins("P15")),
("din", 0, Pins("M15")),
("bck", 0, Pins("L16")),
(
"fast_serial",
0,
Subsignal("di", Pins("B10")),
Subsignal("clk", Pins("B12")),
Subsignal("do", Pins("B13")),
Subsignal("cts", Pins("A15")),
IOStandard("LVCMOS33"),
),
])
plat.add_source("pll_test.v")
plat.build(Top(plat))
plat.create_programmer().load_bitstream("build/top.bin")
elif sys.argv[1] == "prog":
from migen.build.platforms import ice40_hx8k_b_evn
plat = ice40_hx8k_b_evn.Platform()
plat.create_programmer().load_bitstream("build/top.bin")
def __init__(self, **kwargs):
super().__init__(**kwargs)
super().__getattribute__("add_extension")([
("ps", 0, Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33")),
Subsignal("por_b", Pins("C7"), IOStandard("LVCMOS33")),
Subsignal("srst_b", Pins("B10"), IOStandard("LVCMOS18"))),
("ddr", 0,
Subsignal("a",
Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")),
Subsignal("cke", Pins("N3"), IOStandard("SSTL15")),
Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15")),
Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15")),
Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")),
Subsignal("dm", Pins("A1 F1 T1 Y1"), IOStandard("SSTL15_T_DCI")),
Subsignal(
"dq",
Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1 "
"P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n", Pins("B2 F2 T2 W4"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("C2 G2 R2 W5"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15")),
Subsignal("odt", Pins("N5"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI")),
Subsignal("we_n", Pins("M5"), IOStandard("SSTL15"))),
])
_io = [
("sysclk", 0, Pins_s(1)),
("sys_reset", 1, Pins_s(1)),
("clk", 0, Pins_s(1)),
("reset", 0, Pins_s(1)),
("rtiox4", 0, Pins_s(1)),
("irq", 0, Pins_s(32)),
("quantum_cmd", 0, Pins_s(1)),
("quantum_valid", 0, Pins_s(1)),
# model "PHY" pads
(
"model_eth",
0,
Subsignal("source_valid", Pins_s(1)),
Subsignal("source_data", Pins_s(8)),
Subsignal("sink_valid", Pins_s(1)),
Subsignal(
"sink_data",
Pins_s(8),
),
),
# Wishbone
("wishbone", 0, Subsignal("adr",
Pins_s(30)), Subsignal("dat_r", Pins_s(32)),
Subsignal("dat_w", Pins_s(32)), Subsignal("sel", Pins_s(4)),
Subsignal("cyc", Pins_s(1)), Subsignal("stb", Pins_s(1)),
Subsignal("ack", Pins_s(1)), Subsignal("we", Pins_s(1)),
Subsignal("cti",
def __init__(self, **kwargs):
super().__init__(**kwargs)
super().__getattribute__("add_extension")([
("ps", 0, Subsignal("clk", Pins("A22"), IOStandard("LVCMOS18")),
Subsignal("por_b", Pins("D21"), IOStandard("LVCMOS18")),
Subsignal("srst_b", Pins("B19"), IOStandard("LVCMOS18"))),
("ddr", 0,
Subsignal(
"dq",
Pins(
"A25 E25 B27 D25 B25 E26 D26 E27 A29 A27 A30 A28 C28 D30 D28 D29 "
"H27 G27 H28 E28 E30 F28 G30 F30 J29 K27 J30 J28 K30 M29 L30 M30"
), IOStandard("SSTL15_T_DCI")),
Subsignal("dm", Pins("C27 B30 H29 K28"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n", Pins("B26 B29 F29 L29"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("C26 C29 G29 L28"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal(
"a",
Pins(
"L25 K26 L27 G25 J26 G24 H26 K22 F27 J23 G26 H24 K23 H23 J24"
), IOStandard("SSTL15")),
Subsignal("ba", Pins("M27 M26 M25"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("M24"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("N21"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("M21"), IOStandard("SSTL15_T_DCI")),
Subsignal("ras_n", Pins("N24"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("N23"), IOStandard("SSTL15")),
Subsignal("odt", Pins("L23"), IOStandard("SSTL15")),
Subsignal("cke", Pins("M22"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("N22"), IOStandard("SSTL15")),
Subsignal("clk_n", Pins("J25"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("K25"), IOStandard("DIFF_SSTL15")),
Subsignal("reset_n", Pins("F25"), IOStandard("SSTL15"))),
])
_io = [
# numbers are for multiple channels, not really used,
# TODO: wrap polygon in one and laser in one
("gpio14", 0, Pins("113"), IOStandard("LVCMOS33")),
("gpio15", 0, Pins("112"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("61"), IOStandard("LVCMOS33")),
("led2", 0, Pins("8"), IOStandard("LVCMOS33")),
("led3", 0, Pins("3"), IOStandard("LVCMOS33")),
("laser0", 0, Pins("134"), IOStandard("LVCMOS33")),
("laser1", 0, Pins("135"), IOStandard("LVCMOS33")),
("photodiode", 0, Pins("137"), IOStandard("LVCMOS33")),
("poly_en", 0, Pins("141"), IOStandard("LVCMOS33")),
("poly_ready", 0, Pins("138"), IOStandard("LVCMOS33")), # not used
("poly_pwm", 0, Pins("139"), IOStandard("LVCMOS33")),
("spi", 0, Subsignal('cs_n', Pins("85")), Subsignal('miso', Pins("87")),
Subsignal('mosi',
Pins("90")), Subsignal('clk',
Pins("79")), IOStandard("LVCMOS33"))
]
_connectors = []
class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 10
default_clk_freq = 100 # MHz
def __init__(self):
LatticePlatform.__init__(self,
"ice40-hx8k-tq144:4k",
from migen import Module, Signal
from migen.build.lattice import LatticePlatform
from migen.build.generic_platform import Pins, IOStandard, Misc, Subsignal
# Pinouts for various Fomu variants.
_io_evt = [
("serial", 0,
Subsignal("rx", Pins("21")),
Subsignal("tx", Pins("13"), Misc("PULLUP")),
IOStandard("LVCMOS33")
),
("usb", 0,
Subsignal("d_p", Pins("34")),
Subsignal("d_n", Pins("37")),
Subsignal("pullup", Pins("35")),
Subsignal("pulldown", Pins("36")),
IOStandard("LVCMOS33")
),
("touch", 0,
Subsignal("t1", Pins("48"), IOStandard("LVCMOS33")),
Subsignal("t2", Pins("47"), IOStandard("LVCMOS33")),
Subsignal("t3", Pins("46"), IOStandard("LVCMOS33")),
Subsignal("t4", Pins("45"), IOStandard("LVCMOS33")),
),
("pmoda", 0,
Subsignal("p1", Pins("28"), IOStandard("LVCMOS33")),
Subsignal("p2", Pins("27"), IOStandard("LVCMOS33")),
Subsignal("p3", Pins("26"), IOStandard("LVCMOS33")),
Subsignal("p4", Pins("23"), IOStandard("LVCMOS33")),
),
def __init__(self, **kwargs):
super().__init__(**kwargs)
super().__getattribute__("add_extension")([
("ps", 0,
Subsignal("clk", Pins("F7"), IOStandard("LVCMOS33")),
Subsignal("por_b", Pins("B5"), IOStandard("LVCMOS33")),
Subsignal("srst_b", Pins("C9"), IOStandard("LVCMOS18"))),
("ddr", 0,
Subsignal("a",
Pins("M4 M5 K4 L4 K6 K5 J7 J6 J5 H5 J3 G5 H4 F4 G4"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L7 L6 M6"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("P3"), IOStandard("SSTL15")),
Subsignal("cke", Pins("V3"), IOStandard("SSTL15")),
Subsignal("ck_n", Pins("N5"), IOStandard("DIFF_SSTL15")),
Subsignal("ck_p", Pins("N4"), IOStandard("DIFF_SSTL15")),
Subsignal("cs_n", Pins("P6"), IOStandard("SSTL15")),
Subsignal("dm", Pins("B1 H3 P1 AA2"), IOStandard("SSTL15_T_DCI")),
Subsignal("dq",
Pins("D1 C3 B2 D3 E3 E1 F2 F1 G2 G1 L1 L2 L3 K1 J1 K3 "
"M1 T3 N3 T1 R3 T2 M2 R1 AA3 U1 AA1 U2 W1 Y3 W3 Y1"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_n",
Pins("D2 J2 P2 W2"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("dqs_p",
Pins("C2 H2 N2 V2"),
IOStandard("DIFF_SSTL15_T_DCI")),
Subsignal("drst_n", Pins("F3"), IOStandard("SSTL15")),
Subsignal("odt", Pins("P5"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("R5"), IOStandard("SSTL15")),
Subsignal("vrn", Pins("M7"), IOStandard("SSTL15_T_DCI")),
Subsignal("vrp", Pins("N7"), IOStandard("SSTL15_T_DCI")),
Subsignal("we_n", Pins("R4"), IOStandard("SSTL15"))),
])
("clk3_50", 0, Pins("E11"), IOStandard("3.3-V LVTTL")),
("user_led", 0, Pins("W15"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("AA24"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("V16"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("V15"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("AF26"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("AE26"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("Y16"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("AA23"), IOStandard("3.3-V LVTTL")),
("key", 0, Pins("AH17"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("AH16"), IOStandard("3.3-V LVTTL")),
("sw", 0, Pins("L10"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("L9"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("H6"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("H5"), IOStandard("3.3-V LVTTL")),
("epcs", 0, Subsignal("data0",
Pins("AD7")), Subsignal("data1", Pins("AC6")),
Subsignal("data2", Pins("AC5")), Subsignal("data3", Pins("AB6")),
Subsignal("dclk", Pins("AA8")), Subsignal("ncso", Pins("AA6")),
IOStandard("3.3-V LVTTL")),
("adc", 0, Subsignal("convst", Pins("U9")), Subsignal("sck", Pins("V10")),
Subsignal("sdi", Pins("AC4")), Subsignal("sdo", Pins("AD4")),
IOStandard("3.3-V LVTTL")),
("gpio_0", 0,
Pins("V12 AF7 W12 AF8 Y8 AB4 W8 Y4 Y5 U11 T8 T12 AH5 AH6 AH4 AG5 AH3",
"AH2 AF4 AG6 AF5 AE4 T13 T11 AE7 AF6 AF9 AE8 AD10 AE9 AD11 AF10",
"AD12 AE11 AF11 AE12"), IOStandard("3.3-V LVTTL")),
("gpio_1", 0,
Pins("Y15 AG28 AA15 AH27 AG26 AH24 AF23 AE22 AF21 AG20 AG19 AF20",
"AC23 AG18 AH26 AA19 AG24 AF25 AH23 AG23 AE19 AF18 AD19 AE20",
"AE24 AD20 AF22 AH22 AH19 AH21 AG21 AH18 AD23 AE23 AA18 AC22"),
IOStandard("3.3-V LVTTL")),
from migen.build.generic_platform import Subsignal, Pins, IOStandard
from migen.build.lattice import LatticePlatform
from migen.build.lattice.programmer import MyStormProgrammer
_io = [
("sram", 0,
Subsignal("adr", Pins("137 138 139 141 142 42 43 44 73 74 75 76 115",
"116 117 118 119 78")),
Subsignal("dat", Pins("136 135 134 130 125 124 122 121 62 61 60 56 55",
"48 47 45")),
Subsignal("oe", Pins("29")),
Subsignal("we", Pins("120")),
Subsignal("cs", Pins("23")),
Subsignal("ub", Pins("28")),
Subsignal("lb", Pins("24")),
IOStandard("LVCMOS33"),
),
("clk100", 0, Pins("129"), IOStandard("LVCMOS33")),
("mmc", 0,
Subsignal("dat", Pins("63 64 39 38")),
Subsignal("cmd", Pins("41")),
Subsignal("clk", Pins("37")),
IOStandard("LVCMOS33"),
),
("serial", 0,
Subsignal("rx", Pins("88")),
Subsignal("tx", Pins("85")),
from migen.build.generic_platform import Subsignal, Pins, IOStandard
from migen.build.lattice import LatticePlatform
from migen.build.lattice.programmer import MyStormProgrammer
_io = [
(
"sram",
0,
Subsignal(
"adr",
Pins("137 138 139 141 142 42 43 44 73 74 75 76 115",
"116 117 118 119 78 62")),
Subsignal(
"dat",
Pins("135 134 130 128 125 124 122 121 61 60 56 55 52",
"49 48 47")),
Subsignal("oe", Pins("45")),
Subsignal("we", Pins("120")),
Subsignal("cs", Pins("136")),
IOStandard("LVCMOS33"),
),
("clk100", 0, Pins("129"), IOStandard("LVCMOS33")),
(
"mmc",
0,
Subsignal("dat", Pins("63 64 39 38")),
Subsignal("cmd", Pins("41")),
Subsignal("clk", Pins("37")),
IOStandard("LVCMOS33"),
),
(