def __init__(self, hw_rev="v1.0"): if hw_rev == "v1.0": io_rev = _io_v1_0 elif hw_rev == "v1.1": io_rev = _io_v1_1 else: raise ValueError("Unknown hardware revision", hw_rev) XilinxPlatform.__init__(self, "xc7a100t-fgg484-2", _io_common + io_rev, _connectors, toolchain="vivado") self.add_platform_command( "set_property INTERNAL_VREF 0.750 [get_iobanks 35]") self.toolchain.bitstream_commands.extend([ # NOTE: disable this on Kasli/v1.0 boards where the XADC reference # has not been fixed. "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]", "set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]", "set_property BITSTREAM.CONFIG.USERID \"{:#010x}\" [current_design]" .format(self.userid), "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 2.5 [current_design]", ])
def __init__(self): XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io) self.add_platform_command(""" CONFIG VCCAUX = "3.3"; """) self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4" self.toolchain.ise_commands = """
def __init__(self): self.clock_period = CmodA735t.default_clk_period self.clock_rate = 12e6 self.prog_cmd = "djtgcfg prog --verbose -d CmodA7 -i 0 -f ./.migen/p2.bit" XilinxPlatform.__init__( self, "xc7a35tcpg236-1", [ genio("sysclock", "L17", "LVCMOS33"), # 100mhz xtal genio("sw0", "V8", "LVCMOS33"), # PIO48 genio("led0", "A17", "LVCMOS33"), genio("led1", "C16", "LVCMOS33"), genio("ledR", "B17", "LVCMOS33"), genio("ledG", "B16", "LVCMOS33"), genio("ledB", "C17", "LVCMOS33"), genio("pc_tx", "J17", "LVCMOS33"), # uart <- usb genio("pc_rx", "J18", "LVCMOS33"), # uart -> usb genio("pmodA0", "G17", "LVCMOS33"), # pmod pin1 genio("pmodA1", "G19", "LVCMOS33"), # pmod pin2 genio("pmodA2", "N18", "LVCMOS33"), # pmod pin3 genio("pmodA3", "L18", "LVCMOS33"), # pmod pin4 genio("pmodA4", "H17", "LVCMOS33"), # pmod pin7 genio("pmodA5", "H19", "LVCMOS33"), # pmod pin8 genio("pmodA6", "J19", "LVCMOS33"), # pmod pin9 genio("pmodA7", "K18", "LVCMOS33"), # pmod pin10 genio("gpio0", "M3", "LVCMOS33"), # PIO1 genio("gpio1", "L3", "LVCMOS33"), # PIO2 genio("gpio2", "A16", "LVCMOS33"), # PIO3 genio("gpio3", "K3", "LVCMOS33"), # PIO4 genio("gpio4", "C15", "LVCMOS33"), # PIO5 genio("gpio5", "L3", "LVCMOS33"), # PIO6 genio("gpio6", "H1", "LVCMOS33"), # PIO7 genio("gpio7", "B15", "LVCMOS33"), # PIO8 ], toolchain="vivado")
def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) self.add_platform_command(""" TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns; """) try: ifclk = self.lookup_request("fx2_ifclk") gpif = self.lookup_request("fx2_gpif") for i, d in [(gpif.d, "in"), (gpif.d, "out"), (gpif.ctl, "in"), (gpif.adr, "out"), (gpif.slwr, "out"), (gpif.sloe, "out"), (gpif.slrd, "out"), (gpif.pktend, "out")]: if len(i) > 1: q = "(*)" else: q = "" self.add_platform_command(""" INST "{i}%s" TNM = gpif_net_%s; """ % (q, d), i=i) self.add_platform_command(""" NET "{ifclk}" TNM_NET = "GRPifclk"; TIMESPEC "TSifclk" = PERIOD "GRPifclk" 20833 ps HIGH 50%; TIMEGRP "gpif_net_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "{ifclk}" RISING; TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "{ifclk}" RISING; """, ifclk=ifclk) except ConstraintError: pass
def __init__(self, hw_rev="v1.0"): if hw_rev == "v1.0": io_rev = _io_v1_0 elif hw_rev == "v1.1": io_rev = _io_v1_1 else: raise ValueError("Unknown hardware revision", hw_rev) XilinxPlatform.__init__( self, "xc7a100t-fgg484-2", _io_common + io_rev, _connectors, toolchain="vivado") self.add_platform_command( "set_property INTERNAL_VREF 0.750 [get_iobanks 35]") self.toolchain.bitstream_commands.extend([ # NOTE: disable this on Kasli/v1.0 boards where the XADC reference # has not been fixed. "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]", "set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]", "set_property BITSTREAM.CONFIG.USERID \"{:#010x}\" [current_design]".format(self.userid), "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 2.5 [current_design]", ])
def __init__(self): self.clock_period = ArtyA735t.default_clk_period self.clock_rate = 1e11 / ArtyA735t.default_clk_period self.prog_cmd = "djtgcfg prog --verbose -d Arty -i 0 -f ./.migen/p2.bit" XilinxPlatform.__init__( self, "xc7a35ticsg324-1L", [ genio("sysclock", "E3", "LVCMOS33"), # 100mhz xtal genio("sw0", "A8", "LVCMOS33"), # SW0 genio("led0", "H5", "LVCMOS33"), # LD4 genio("led1", "J5", "LVCMOS33"), # LD5 genio("led2", "T9", "LVCMOS33"), # LD6 genio("led3", "T10", "LVCMOS33"), # LD7 genio("led4", "J4", "LVCMOS33"), # LD1g genio("ledR", "G6", "LVCMOS33"), # LD0r genio("ledG", "F6", "LVCMOS33"), # LD0g genio("ledB", "E1", "LVCMOS33"), # LD0b genio("pc_tx", "A9", "LVCMOS33"), genio("pc_rx", "D10", "LVCMOS33"), genio("pmod1", "G17", "LVCMOS33"), genio("pmod2", "G19", "LVCMOS33"), genio("gpioX", "XX", "LVCMOS33"), # PIO1 genio("gpioY", "XX", "LVCMOS33"), # PIO2 ], toolchain="vivado")
def __init__(self): XilinxPlatform.__init__(self, "xc7a100t-fgg484-2", _io, _connectors, toolchain="vivado") self.add_platform_command( "set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def __init__(self): XilinxPlatform.__init__(self, "xc7a15t-csg325-1", _io, toolchain="vivado") self.toolchain.bitstream_commands.extend([ # FIXME: enable this when the XADC reference wiring is fixed # "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 3.3 [current_design]", ])
def __init__(self, toolchain="vivado", programmer="vivado", device="xc7a35ticsg324-1L"): XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ ["write_cfgmem -force -format bin -interface spix4 -size 16 " "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.programmer = programmer self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def __init__(self, toolchain="vivado", programmer="xc3sprog"): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain=toolchain) if toolchain == "ise": self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" elif toolchain == "vivado": self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.programmer = programmer
def __init__(self): XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, toolchain="vivado") self.toolchain.pre_synthesis_commands.append( "read_xdc -ref processing_system7_v5_4_processing_system7 ../verilog/system_processing_system7_0_0.xdc" ) self.toolchain.with_phys_opt = True
def __init__(self, load=False, flash=False): XilinxPlatform.__init__(self, "xc7a100t-fgg484-2", _ios, _connectors, toolchain="vivado") self.add_extension(_extensions) self.add_platform_command( "set_property INTERNAL_VREF 0.750 [get_iobanks 35]") self.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN " "Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property BITSTREAM.CONFIG.USR_ACCESS " "TIMESTAMP [current_design]", "set_property BITSTREAM.CONFIG.USERID " "\"{:#010x}\" [current_design]".format(self.userid), "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 2.5 [current_design]", ]) if load or flash: self.toolchain.additional_commands.extend([ "open_hw_manager", "connect_hw_server", "open_hw_target", "current_hw_device [lindex [get_hw_devices] 0]", ] + ([ "write_cfgmem -force -format MCS -size 8 -interface SPIx4 " "-loadbit \"up 0x0 {build_name}.bit\" {build_name}", "create_hw_cfgmem -hw_device [current_hw_device] " "[lindex [get_cfgmem_parts " "{{s25fl128sxxxxxx0-spi-x1_x2_x4}}] 0]", "set_property PROGRAM.BLANK_CHECK 0 [current_hw_cfgmem]", "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]", "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]", "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]", "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]", "set_property PROGRAM.ADDRESS_RANGE " "{{use_file}} [current_hw_cfgmem]", "set_property PROGRAM.FILES " "{{{build_name}.mcs}} [current_hw_cfgmem]", "set_property PROGRAM.UNUSED_PIN_TERMINATION " "{{pull-none}} [current_hw_cfgmem]", "create_hw_bitstream -hw_device [current_hw_device] " "[get_property PROGRAM.HW_CFGMEM_BITFILE " "[current_hw_device]]", "program_hw_devices", "program_hw_cfgmem", "boot_hw_device -verbose [current_hw_device]" ] if flash else [ "set_property PROGRAM.FILE {{{build_name}.bit}} " "[current_hw_device]", "program_hw_devices", # "refresh_hw_device", ]) + ["close_hw_target", "close_hw_manager"])
def __init__(self, larger=False): chip = "xc7a50t-csg325-3" if larger else "xc7a35t-csg325-3" XilinxPlatform.__init__(self, chip, _io, toolchain="vivado", name="sayma_rtm") self.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 3.3 [current_design]", ])
def __init__(self): XilinxPlatform.__init__(self, "xczu28dr-ffvg1517-2-e", _io, _connectors, toolchain="vivado") # crowbar project command to add BOARD_PART in order to avoid IP warnings/errors upon import self.toolchain.project_commands = [ "set_property BOARD_PART xilinx.com:zcu111:part0:1.1 [current_project]" ]
def __init__(self, toolchain="vivado", programmer="vivado"): XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ ["write_cfgmem -force -format bin -interface spix4 -size 16 " "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.programmer = programmer self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def __init__(self): XilinxPlatform.__init__(self, "xc3s500e-4pq208", _io) self.toolchain.xst_opt = """-ifmt MIXED -bram_utilization_ratio -1 -opt_level 2 -opt_mode SPEED -register_balancing yes""" self.toolchain.bitgen_opt += (" -g GTS_cycle:3 -g LCK_cycle:4 " "-g GWE_cycle:5 -g DONE_cycle:6") self.toolchain.ise_commands += """
def __init__(self): chip = "xc7a50t-csg325-3" XilinxPlatform.__init__(self, chip, _io, toolchain="vivado", name="sayma_rtm") self.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 3.3 [current_design]", ])
def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) try: self.add_period_constraint( self.lookup_request("eth_clocks").rx, 8.0) except ConstraintError: pass try: self.add_period_constraint( self.lookup_request("eth_clocks").tx, 8.0) except ConstraintError: pass
def __init__(self): XilinxPlatform.__init__( self, "xc7a200tffg1156-3", _io, _connectors, toolchain="vivado") self.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", "set_property CONFIG_MODE SPIx1 [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 2.5 [current_design]", ])
def __init__(self): XilinxPlatform.__init__( self, "xcku040-ffva1156-1-c", _io, _connectors, toolchain="vivado", name="sayma_amc") self.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 3.3 [current_design]", ])
def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) try: eth_clocks = self.lookup_request("eth_clocks") self.add_period_constraint(eth_clocks.rx, 40) self.add_period_constraint(eth_clocks.tx, 40) self.add_platform_command(""" TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns; TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns; """, phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx) except ConstraintError: pass
def __init__(self): XilinxPlatform.__init__( self, "xcku040-ffva1156-1-c", _io, _connectors, toolchain="vivado") self.toolchain.bitstream_commands.extend([ # FIXME: enable this when the XADC reference wiring is fixed # "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 3.3 [current_design]", ])
def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) try: self.add_period_constraint(self.lookup_request("clk200").p, 5.0) except ConstraintError: pass try: self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) except ConstraintError: pass if isinstance(self.toolchain, XilinxISEToolchain): self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";") else: self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) try: clk_if = self.lookup_request("clk_if") clk_fx = self.lookup_request("clk_fx") self.add_platform_command(""" NET "{clk_if}" TNM_NET = "GRPclk_if"; NET "{clk_fx}" TNM_NET = "GRPclk_fx"; TIMESPEC "TSclk_fx" = PERIOD "GRPclk_fx" 20.83333 ns HIGH 50%; TIMESPEC "TSclk_if" = PERIOD "GRPclk_if" 20 ns HIGH 50%; TIMESPEC "TSclk_fx2if" = FROM "GRPclk_fx" TO "GRPclk_if" 3 ns DATAPATHONLY; TIMESPEC "TSclk_if2fx" = FROM "GRPclk_if" TO "GRPclk_fx" 3 ns DATAPATHONLY; """, clk_if=clk_if, clk_fx=clk_fx) except ConstraintError: pass
def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) try: self.add_period_constraint(self.lookup_request("clk200").p, 5.0) except ConstraintError: pass try: self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0) except ConstraintError: pass try: self.add_period_constraint(self.lookup_request("eth_clocks").tx, 8.0) except ConstraintError: pass if isinstance(self.toolchain, XilinxISEToolchain): self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";") else: self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def __init__(self): XilinxPlatform.__init__( self, "xc7a100t-fgg484-2", _ios, _connectors, toolchain="vivado") self.add_extension(_extensions) self.add_platform_command( "set_property INTERNAL_VREF 0.750 [get_iobanks 35]") self.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN " "Enable [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", "set_property BITSTREAM.CONFIG.USR_ACCESS " "TIMESTAMP [current_design]", "set_property BITSTREAM.CONFIG.USERID " "\"{:#010x}\" [current_design]".format(self.userid), "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 2.5 [current_design]", ])
def __init__(self, hw_rev="v1.0"): if hw_rev == "v1.0": io_rev = _io_v1_0 elif hw_rev == "v1.1": io_rev = _io_v1_1 else: raise ValueError("Unknown hardware revision", hw_rev) XilinxPlatform.__init__(self, "xc7a100t-fgg484-2", _io_common + io_rev, _connectors, toolchain="vivado") self.add_platform_command( "set_property INTERNAL_VREF 0.750 [get_iobanks 35]") self.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]", "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design]", "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 2.5 [current_design]", ])
def __init__(self): self.clock_period = Nexys4.default_clk_period self.clock_rate = 100e6 self.prog_cmd = "djtgcfg prog --verbose -d Nexys4 -i 0 -f ./.migen/p2.bit" XilinxPlatform.__init__( self, "xc7a100t-CSG324-1", [ genio("sysclock", "E3", "LVCMOS33"), # 100mhz xtal genio("sw0", "U9", "LVCMOS33"), # SW0 genio("led0", "T8", "LVCMOS33"), genio("led1", "V9", "LVCMOS33"), genio("led2", "R8", "LVCMOS33"), genio("led3", "T6", "LVCMOS33"), genio("led4", "T5", "LVCMOS33"), genio("ledR", "K6", "LVCMOS33"), genio("ledG", "H6", "LVCMOS33"), genio("ledB", "L16", "LVCMOS33"), genio("pc_tx", "C4", "LVCMOS33"), genio("pc_rx", "D4", "LVCMOS33"), genio("pmodA0", "B13", "LVCMOS33"), # PMOD JA1 genio("pmodA1", "F14", "LVCMOS33"), # PMOD JA2 genio("pmodA2", "D17", "LVCMOS33"), # PMOD JA3 genio("pmodA3", "E17", "LVCMOS33"), # PMOD JA4 genio("pmodA4", "G13", "LVCMOS33"), # PMOD JA7 genio("pmodA5", "C17", "LVCMOS33"), # PMOD JA8 genio("pmodA6", "D18", "LVCMOS33"), # PMOD JA9 genio("pmodA7", "E18", "LVCMOS33"), # PMOD JA10 genio("gpio0", "G14", "LVCMOS33"), # PMOD JB1 genio("gpio1", "P15", "LVCMOS33"), # PMOD JB2 genio("gpio2", "V11", "LVCMOS33"), # PMOD JB3 genio("gpio3", "V15", "LVCMOS33"), # PMOD JB4 genio("gpio4", "K16", "LVCMOS33"), # PMOD JB7 genio("gpio5", "R16", "LVCMOS33"), # PMOD JB8 genio("gpio6", "T9", "LVCMOS33"), # PMOD JB9 genio("gpio7", "U11", "LVCMOS33"), # PMOD JB10 ], toolchain="vivado")
def __init__(self, board_type: str): _connectors = [] fpga_part = "" # Board types if board_type == "xc7a100t_ddr3": _io = _io_100t_ddr3 _connectors = _connectors_100t_ddr3 fpga_part = "xc7a100tfgg676" elif board_type == "xc7a35t_ddr3": _io = _io_35t_ddr3 _connectors = _connectors_35t_ddr3 fpga_part = "xc7a35tftg256-1" else: raise ValueError('Please select a valid board') XilinxPlatform.__init__(self, fpga_part, _io, _connectors, toolchain="vivado") self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
def __init__(self): self.clock_period = Sim1mhz.default_clk_period self.clock_rate = 0.01e6 print("ClockPeriod<%f ns>" % self.clock_period) print("ClockRate<%f Mhz>" % (self.clock_rate / 1e6)) self.prog_cmd = "djtgcfg prog --verbose -d CmodA7 -i 0 -f ./.migen/p2.bit" XilinxPlatform.__init__( self, "xc7a35tcpg236-1", [ genio("sysclock", "L17", "LVCMOS33"), # 100mhz xtal genio("sw0", "M3", "LVCMOS33"), # PIO0 genio("led0", "A17", "LVCMOS33"), genio("led1", "C16", "LVCMOS33"), genio("ledR", "B17", "LVCMOS33"), genio("ledG", "B16", "LVCMOS33"), genio("ledB", "C17", "LVCMOS33"), genio("pc_tx", "J17", "LVCMOS33"), genio("pc_rx", "J18", "LVCMOS33"), genio("pmodA0", "G17", "LVCMOS33"), genio("pmodA1", "G19", "LVCMOS33"), genio("pmodA2", "N18", "LVCMOS33"), genio("pmodA3", "L18", "LVCMOS33"), genio("pmodA4", "H17", "LVCMOS33"), genio("pmodA5", "H19", "LVCMOS33"), genio("pmodA6", "J19", "LVCMOS33"), genio("pmodA7", "K18", "LVCMOS33"), genio("gpio0", "M3", "LVCMOS33"), # PIO1 genio("gpio1", "L3", "LVCMOS33"), # PIO2 genio("gpio2", "A16", "LVCMOS33"), # PIO3 genio("gpio3", "K3", "LVCMOS33"), # PIO4 genio("gpio4", "C15", "LVCMOS33"), # PIO5 genio("gpio5", "L3", "LVCMOS33"), # PIO6 genio("gpio6", "H1", "LVCMOS33"), # PIO7 genio("gpio7", "B15", "LVCMOS33"), # PIO8 ], toolchain="vivado")
def __init__(self): XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io) self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
def __init__(self): XilinxPlatform.__init__( self, "xc7a100t-fgg484-2", _io, _connectors, toolchain="vivado") self.add_platform_command( "set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def __init__(self): XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, _connectors)
def __init__(self): XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io) self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
def __init__(self): XilinxPlatform.__init__(self, "xc6slx9-tqg144-3", _io)
def __init__(self, device="xc3s200a-4-vq100"): XilinxPlatform.__init__(self, device, _io, _connectors) # Small device- optimize for AREA instead of SPEED (LM32 runs at about # 60-65MHz in AREA configuration). self.toolchain.xst_opt = """-ifmt MIXED
def __init__(self): XilinxPlatform.__init__(self, "xcku040-ffva1156-1-c", _io, toolchain="vivado")
def __init__(self): XilinxPlatform.__init__(self, "xc6slx16-ftg256", _io, _connectors)
def __init__(self): XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors) self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
def __init__(self): XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io)
def __init__(self): XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io)
def __init__(self): XilinxPlatform.__init__(self, "xc2c128-6-tq144", _io) self.toolchain.xst_opt = "-ifmt MIXED" self.toolchain.par_opt = ("-optimize speed -unused pullup " "-iostd LVCMOS33")
def __init__(self): XilinxPlatform.__init__(self, "xc7a15t-csg325-1", _io, toolchain="vivado")
def __init__(self, device="xc6slx9", programmer="xc3sprog"): self.programmer = programmer XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
def __init__(self): XilinxPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io)
def __init__(self): XilinxPlatform.__init__(self, "xc7z045-ffg900-1", _io, _connectors, toolchain="vivado")
def __init__(self): XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors)
def __init__(self): XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado")
def __init__(self): XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io)