def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None): from migen.fhdl.size import bits_for Value.__init__(self) # determine number of bits and signedness if bits_sign is None: if min is None: min = 0 if max is None: max = 2 max -= 1 # make both bounds inclusive assert(min < max) self.signed = min < 0 or max < 0 self.nbits = builtins.max(bits_for(min, self.signed), bits_for(max, self.signed)) else: assert(min is None and max is None) if isinstance(bits_sign, tuple): self.nbits, self.signed = bits_sign else: self.nbits, self.signed = bits_sign, False assert(isinstance(self.nbits, int)) self.variable = variable self.reset = reset self.name_override = name_override self.backtrace = tracer.trace_back(name)
def _printintbool(node): if isinstance(node, bool): if node: return "1'd1", False else: return "1'd0", False elif isinstance(node, int): if node >= 0: return str(bits_for(node)) + "'d" + str(node), False else: return "-" + str(bits_for(node)) + "'sd" + str(-node), True else: raise TypeError
def __init__(self): from migen.actorlib.sim import SimActor, Dumper, Token class PORT(Module): def __init__(self, aw, dw): self.adr = Signal(aw) self.dat_r = Signal(dw) self.sync += self.dat_r.eq(self.adr) self.submodules.port = PORT(bits_for(1024), 8) def gen(): yield Token('source', {"start": 0, "count" : 4}) yield None yield Token('source', {"start": 555, "count" : 77}) class SimSource(SimActor): def __init__(self): self.source = Source(dmatpl(1024)) SimActor.__init__(self, gen()) self.submodules.src = SimSource() self.submodules.c = Consumer(self.port, 1024) self.comb += self.c.sink.connect(self.src.source) self.comb += self.src.busy.eq(0) self.submodules.dmp = Dumper(D_LAST) self.comb += self.c.source.connect(self.dmp.result) self.comb += self.dmp.busy.eq(0)
def dmatpl(depth): b = bits_for(depth-1) return [('start', b), ('count', b)]
def __init__(self): from migen.actorlib.sim import SimActor, Dumper, Token class PORT(Module): def __init__(self, aw, dw): self.adr = Signal(aw) self.dat_w = Signal(dw) self.we = Signal(1) import array self.mem = array.array('B', [0] * 2**aw) def do_simulation(self, s): writing, w_addr, w_data = s.multiread([self.we, self.adr, self.dat_w]) if writing: assert w_addr < 1024 self.mem[w_addr] = w_data self.submodules.port = PORT(bits_for(1024), 8) def packet(size=0, st=0, end=1): yield Token('source', {'rxcmd':1, 'd':0x40}) for i in range(size): yield Token('source', {'rxcmd':0, 'd':(i+st)&0xFF}) if end != 4: yield Token('source', {'rxcmd':1, 'd':0x40 | end}) print("Complete") def gen(): for i in packet(530, 0, 1): yield i for i in packet(530, 0x10, 1): yield i for i in packet(10, 0x20, 4): yield i for i in packet(10, 0x30, 2): yield i for i in packet(900, 0x30, 4): yield i for i in packet(10, 0x30, 2): yield i class SimSource(SimActor): def __init__(self): self.source = Source(ULPI_DATA) SimActor.__init__(self, gen()) class SimDMASink(SimActor): def __init__(self, mem, cw): self.sink = Sink(dmatpl(1024)) SimActor.__init__(self, self.gen()) self.mem = mem self.cw = cw def gen(self): import constants _fn = {} for k,v in constants.__dict__.items(): if k.startswith("HF0_"): _fn[v] = k[4:] while 1: t = Token('sink') yield t # Long delay between packet readout for i in range(600): yield None print("DMAFROM: %04x (%02x)" % (t.value['start'], t.value['count'])) i = t.value['start'] psize = self.mem[i+3] | self.mem[i+4] << 8 pflags = self.mem[i+1] | self.mem[i+2] e = [] for i in range(0,16): if pflags & 1<<i and 1<<i in _fn: e.append(_fn[1<<i]) print("\tFlag: %s" % ", ".join(e)) d = [self.mem[i%1024] for i in range(t.value['start'], t.value['start'] + t.value['count'])] print("\t%s" % " ".join("%02x" % i for i in d)) assert t.value['count'] == psize + 8 self.s.wr(self.cw, (t.value['start'] + t.value['count']) & (1024-1)) b = d[8] rem = d[9:] c = [(i+b+1) & 0xFF for i in range(0, len(rem))] assert c == rem print() def do_simulation(self, s): SimActor.do_simulation(self, s) self.s = s self.consume_watermark =Signal(max=1024) self.submodules.src = SimSource() self.submodules.p = Producer(self.port, 1024, self.consume_watermark) self.comb += self.p.ulpi_sink.connect(self.src.source) self.comb += self.src.busy.eq(0) self.submodules.dmp = SimDMASink(self.port.mem, self.consume_watermark) self.comb += self.p.out_addr.connect(self.dmp.sink) self.comb += self.dmp.busy.eq(0)
def emit_verilog(memory, ns): r = "" gn = ns.get_name # usable instead of verilog_printexpr as ports contain only signals adrbits = bits_for(memory.depth - 1) r += "reg [" + str(memory.width - 1) + ":0] " + gn(memory) + "[0:" + str(memory.depth - 1) + "];\n" adr_regs = {} data_regs = {} for port in memory.ports: if not port.async_read: if port.mode == WRITE_FIRST and port.we is not None: adr_reg = Signal(name_override="memadr") r += "reg [" + str(adrbits - 1) + ":0] " + gn(adr_reg) + ";\n" adr_regs[id(port)] = adr_reg else: data_reg = Signal(name_override="memdat") r += "reg [" + str(memory.width - 1) + ":0] " + gn(data_reg) + ";\n" data_regs[id(port)] = data_reg for port in memory.ports: r += "always @(posedge " + gn(port.clock) + ") begin\n" if port.we is not None: if port.we_granularity: n = memory.width // port.we_granularity for i in range(n): m = i * port.we_granularity M = (i + 1) * port.we_granularity - 1 sl = "[" + str(M) + ":" + str(m) + "]" r += "\tif (" + gn(port.we) + "[" + str(i) + "])\n" r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "]" + sl + " <= " + gn(port.dat_w) + sl + ";\n" else: r += "\tif (" + gn(port.we) + ")\n" r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n" if not port.async_read: if port.mode == WRITE_FIRST and port.we is not None: rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n" else: bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n" if port.mode == READ_FIRST or port.we is None: rd = "\t" + bassign elif port.mode == NO_CHANGE: rd = "\tif (!" + gn(port.we) + ")\n" + "\t\t" + bassign if port.re is None: r += rd else: r += "\tif (" + gn(port.re) + ")\n" r += "\t" + rd.replace("\n\t", "\n\t\t") r += "end\n\n" for port in memory.ports: if port.async_read: r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n" else: if port.mode == WRITE_FIRST and port.we is not None: r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n" else: r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n" r += "\n" if memory.init is not None: r += "initial begin\n" for i, c in enumerate(memory.init): r += "\t" + gn(memory) + "[" + str(i) + "] <= " + str(memory.width) + "'d" + str(c) + ";\n" r += "end\n\n" return r