def __init__(self, **kwargs):
_SatelliteBase.__init__(self, **kwargs)
platform = self.platform
rtio_channels = []
phy = ttl_serdes_7series.Output_8X(platform.request("allaki0_rfsw0"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_serdes_7series.Output_8X(platform.request("allaki0_rfsw1"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_rtio(rtio_channels)
# HMC clock chip and DAC control
self.comb += [
platform.request("ad9154_rst_n", 0).eq(1),
platform.request("ad9154_rst_n", 1).eq(1)
]
self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
self.csr_devices.append("converter_spi")
self.submodules.hmc7043_reset = gpio.GPIOOut(
platform.request("hmc7043_reset"), reset_out=1)
self.csr_devices.append("hmc7043_reset")
self.submodules.hmc7043_gpo = gpio.GPIOIn(
platform.request("hmc7043_gpo"))
self.csr_devices.append("hmc7043_gpo")
self.config["HAS_HMC830_7043"] = None
self.config["HAS_AD9154"] = None
self.config["AD9154_COUNT"] = 2
self.config["CONVERTER_SPI_HMC830_CS"] = 0
self.config["CONVERTER_SPI_HMC7043_CS"] = 1
self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
self.config["HMC830_REF"] = "150"
# HMC workarounds
self.comb += platform.request("hmc830_pwr_en").eq(1)
self.submodules.hmc7043_out_en = gpio.GPIOOut(
platform.request("hmc7043_out_en"))
self.csr_devices.append("hmc7043_out_en")
def __init__(self, **kwargs):
_SatelliteBase.__init__(self, **kwargs)
platform = self.platform
rtio_channels = []
for bm in range(2):
print("BaseMod{} RF switches starting at RTIO channel 0x{:06x}"
.format(bm, len(rtio_channels)))
for i in range(4):
phy = ttl_serdes_7series.Output_8X(platform.request("basemod{}_rfsw".format(bm), i),
invert=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}"
.format(bm, len(rtio_channels)))
basemod_att = platform.request("basemod{}_att".format(bm))
for name in "rst_n clk le".split():
signal = getattr(basemod_att, name)
for i in range(len(signal)):
phy = ttl_simple.Output(signal[i])
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.Output(basemod_att.mosi[0])
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(3):
self.comb += basemod_att.mosi[i+1].eq(basemod_att.miso[i])
phy = ttl_simple.InOut(basemod_att.miso[3])
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_rtio(rtio_channels)
self.comb += platform.request("clk_src_ext_sel").eq(0)
# HMC clock chip and DAC control
self.comb += [
platform.request("ad9154_rst_n", 0).eq(1),
platform.request("ad9154_rst_n", 1).eq(1)
]
self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
self.csr_devices.append("converter_spi")
self.submodules.hmc7043_reset = gpio.GPIOOut(
platform.request("hmc7043_reset"), reset_out=1)
self.csr_devices.append("hmc7043_reset")
self.submodules.hmc7043_gpo = gpio.GPIOIn(
platform.request("hmc7043_gpo"))
self.csr_devices.append("hmc7043_gpo")
self.config["HAS_HMC830_7043"] = None
self.config["HAS_AD9154"] = None
self.config["AD9154_COUNT"] = 2
self.config["CONVERTER_SPI_HMC830_CS"] = 0
self.config["CONVERTER_SPI_HMC7043_CS"] = 1
self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
self.config["HMC830_REF"] = str(int(self.rtio_clk_freq/1e6))
# HMC workarounds
self.comb += platform.request("hmc830_pwr_en").eq(1)
self.submodules.hmc7043_out_en = gpio.GPIOOut(
platform.request("hmc7043_out_en"))
self.csr_devices.append("hmc7043_out_en")
# DDMTD
sysref_pads = platform.request("rtm_fpga_sysref", 0)
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
self.csr_devices.append("sysref_ddmtd")
platform.add_false_path_constraints(
self.sysref_ddmtd.cd_helper.clk, self.drtio_transceiver.gtps[0].txoutclk)
platform.add_false_path_constraints(
self.sysref_ddmtd.cd_helper.clk, self.crg.cd_sys.clk)
def __init__(self, platform):
csr_devices = []
self.submodules.crg = CRG(platform)
clk_freq = 125e6
self.submodules.rtm_magic = RTMMagic()
csr_devices.append("rtm_magic")
self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
csr_devices.append("rtm_identifier")
# clock mux: 100MHz ext SMA clock to HMC830 input
self.submodules.clock_mux = gpio.GPIOOut(
Cat(platform.request("clk_src_ext_sel"),
platform.request("ref_clk_src_sel"),
platform.request("dac_clk_src_sel")))
csr_devices.append("clock_mux")
# UART loopback
serial = platform.request("serial")
self.comb += serial.tx.eq(serial.rx)
# Allaki: enable RF output, GPIO access to attenuator
self.comb += [
platform.request("allaki0_rfsw0").eq(1),
platform.request("allaki0_rfsw1").eq(1),
platform.request("allaki1_rfsw0").eq(1),
platform.request("allaki1_rfsw1").eq(1),
platform.request("allaki2_rfsw0").eq(1),
platform.request("allaki2_rfsw1").eq(1),
platform.request("allaki3_rfsw0").eq(1),
platform.request("allaki3_rfsw1").eq(1),
]
allaki_atts = [
platform.request("allaki0_att0"),
platform.request("allaki0_att1"),
platform.request("allaki1_att0"),
platform.request("allaki1_att1"),
platform.request("allaki2_att0"),
platform.request("allaki2_att1"),
platform.request("allaki3_att0"),
platform.request("allaki3_att1"),
]
allaki_att_gpio = []
for allaki_att in allaki_atts:
allaki_att_gpio += [
allaki_att.le,
allaki_att.sin,
allaki_att.clk,
allaki_att.rst_n,
]
self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio))
csr_devices.append("allaki_atts")
# HMC clock chip and DAC control
self.comb += [
platform.request("ad9154_rst_n").eq(1),
platform.request("ad9154_txen", 0).eq(0b11),
platform.request("ad9154_txen", 1).eq(0b11)
]
self.submodules.converter_spi = spi2.SPIMaster(
spi2.SPIInterface(platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0)
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 8.)
serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device,
serwb_pads,
mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += [
self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),
self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset)
]
csr_devices.append("serwb_phy_rtm")
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm,
int(clk_freq),
mode="master")
self.submodules += serwb_core
# process CSR devices and connect them to serwb
self.csr_regions = []
wb_slaves = WishboneSlaveManager(0x10000000)
for i, name in enumerate(csr_devices):
origin = i * CSR_RANGE_SIZE
module = getattr(self, name)
csrs = module.get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
self.csr_regions.append((name, origin, 32, csrs))
self.submodules += wishbone.Decoder(
serwb_core.etherbone.wishbone.bus,
wb_slaves.get_interconnect_slaves(),
register=True)
def __init__(self, platform):
csr_devices = []
self.submodules.crg = CRG(platform)
clk_freq = 125e6
self.submodules.rtm_magic = RTMMagic()
csr_devices.append("rtm_magic")
self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
csr_devices.append("rtm_identifier")
self.submodules.rtm_scratch = RTMScratch()
csr_devices.append("rtm_scratch")
# clock mux: 100MHz ext SMA clock to HMC830 input
self.submodules.clock_mux = gpio.GPIOOut(Cat(
platform.request("clk_src_ext_sel"),
platform.request("ref_clk_src_sel"),
platform.request("dac_clk_src_sel"),
platform.request("ref_lo_clk_sel")),
reset_out=0b0111)
csr_devices.append("clock_mux")
# Allaki: enable RF output, GPIO access to attenuator
self.comb += [
platform.request("allaki0_rfsw0").eq(1),
platform.request("allaki0_rfsw1").eq(1),
platform.request("allaki1_rfsw0").eq(1),
platform.request("allaki1_rfsw1").eq(1),
platform.request("allaki2_rfsw0").eq(1),
platform.request("allaki2_rfsw1").eq(1),
platform.request("allaki3_rfsw0").eq(1),
platform.request("allaki3_rfsw1").eq(1),
]
allaki_atts = [
platform.request("allaki0_att0"),
platform.request("allaki0_att1"),
platform.request("allaki1_att0"),
platform.request("allaki1_att1"),
platform.request("allaki2_att0"),
platform.request("allaki2_att1"),
platform.request("allaki3_att0"),
platform.request("allaki3_att1"),
]
allaki_att_gpio = []
for allaki_att in allaki_atts:
allaki_att_gpio += [
allaki_att.le,
allaki_att.sin,
allaki_att.clk,
allaki_att.rst_n,
]
self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio))
csr_devices.append("allaki_atts")
# HMC clock chip and DAC control
self.comb += platform.request("ad9154_rst_n").eq(1)
self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
csr_devices.append("converter_spi")
self.submodules.hmc7043_reset = gpio.GPIOOut(
platform.request("hmc7043_reset"), reset_out=1)
csr_devices.append("hmc7043_reset")
self.submodules.hmc7043_gpo = gpio.GPIOIn(
platform.request("hmc7043_gpo"))
csr_devices.append("hmc7043_gpo")
# DDMTD
self.clock_domains.cd_rtio = ClockDomain(reset_less=True)
rtio_clock_pads = platform.request("si5324_clkout_fabric")
self.specials += Instance("IBUFGDS", i_I=rtio_clock_pads.p, i_IB=rtio_clock_pads.n,
o_O=self.cd_rtio.clk)
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(
platform.request("rtm_master_aux_clk"), 150e6)
csr_devices.append("sysref_ddmtd")
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk, 8.)
serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += [
self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),
self.crg.serwb_reset.eq(serwb_phy_rtm.serdes.reset)
]
csr_devices.append("serwb_phy_rtm")
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master")
self.submodules += serwb_core
# process CSR devices and connect them to serwb
self.csr_regions = []
wb_slaves = WishboneSlaveManager(0x10000000)
for i, name in enumerate(csr_devices):
origin = i*CSR_RANGE_SIZE
module = getattr(self, name)
csrs = module.get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
self.csr_regions.append((name, origin, 32, csrs))
self.submodules += wishbone.Decoder(serwb_core.etherbone.wishbone.bus,
wb_slaves.get_interconnect_slaves(),
register=True)
def __init__(self, platform):
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
])
csr_devices = []
self.submodules.crg = CRG(platform)
clk_freq = 125e6
self.submodules.rtm_magic = RTMMagic()
csr_devices.append("rtm_magic")
self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
csr_devices.append("rtm_identifier")
# clock mux: 100MHz ext SMA clock to HMC830 input
self.submodules.clock_mux = gpio.GPIOOut(Cat(
platform.request("clk_src_ext_sel"),
platform.request("ref_clk_src_sel"),
platform.request("dac_clk_src_sel")))
csr_devices.append("clock_mux")
# UART loopback
serial = platform.request("serial")
self.comb += serial.tx.eq(serial.rx)
# Allaki: enable RF output, GPIO access to attenuator
self.comb += [
platform.request("allaki0_rfsw0").eq(1),
platform.request("allaki0_rfsw1").eq(1),
platform.request("allaki1_rfsw0").eq(1),
platform.request("allaki1_rfsw1").eq(1),
platform.request("allaki2_rfsw0").eq(1),
platform.request("allaki2_rfsw1").eq(1),
platform.request("allaki3_rfsw0").eq(1),
platform.request("allaki3_rfsw1").eq(1),
]
allaki_atts = [
platform.request("allaki0_att0"),
platform.request("allaki0_att1"),
platform.request("allaki1_att0"),
platform.request("allaki1_att1"),
platform.request("allaki2_att0"),
platform.request("allaki2_att1"),
platform.request("allaki3_att0"),
platform.request("allaki3_att1"),
]
allaki_att_gpio = []
for allaki_att in allaki_atts:
allaki_att_gpio += [
allaki_att.le,
allaki_att.sin,
allaki_att.clk,
allaki_att.rst_n,
]
self.submodules.allaki_atts = gpio.GPIOOut(Cat(*allaki_att_gpio))
csr_devices.append("allaki_atts")
# HMC clock chip and DAC control
self.comb += [
platform.request("ad9154_rst_n").eq(1),
platform.request("ad9154_txen", 0).eq(0b11),
platform.request("ad9154_txen", 1).eq(0b11)
]
self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0)
# AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(62.5e6, 625e6, vco_div=1)
self.submodules += serwb_pll
serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 16.)
serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += self.crg.reset.eq(serwb_phy_rtm.init.reset)
csr_devices.append("serwb_phy_rtm")
serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
serwb_phy_rtm.serdes.cd_serwb_serdes.clk,
serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk)
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True)
self.submodules += serwb_core
# process CSR devices and connect them to serwb
self.csr_regions = []
wb_slaves = WishboneSlaveManager(0x10000000)
for i, name in enumerate(csr_devices):
origin = i*CSR_RANGE_SIZE
module = getattr(self, name)
csrs = module.get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
self.csr_regions.append((name, origin, 32, csrs))
self.submodules += wishbone.Decoder(serwb_core.etherbone.wishbone.bus,
wb_slaves.get_interconnect_slaves(),
register=True)
def __init__(self, **kwargs):
_SatelliteBase.__init__(self, **kwargs)
platform = self.platform
rtio_channels = []
for bm in range(2):
print("BaseMod{} RF switches starting at RTIO channel 0x{:06x}".
format(bm, len(rtio_channels)))
for i in range(4):
phy = ttl_serdes_7series.Output_8X(platform.request(
"basemod{}_rfsw".format(bm), i),
invert=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
print("BaseMod{} attenuator starting at RTIO channel 0x{:06x}".
format(bm, len(rtio_channels)))
basemod_att = platform.request("basemod{}_att".format(bm))
for name in "rst_n clk le".split():
signal = getattr(basemod_att, name)
for i in range(len(signal)):
phy = ttl_simple.Output(signal[i])
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.Output(basemod_att.mosi[0])
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(3):
self.comb += basemod_att.mosi[i + 1].eq(basemod_att.miso[i])
phy = ttl_simple.InOut(basemod_att.miso[3])
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_rtio(rtio_channels)
self.comb += platform.request("clk_src_ext_sel").eq(0)
# HMC clock chip and DAC control
self.comb += [
platform.request("ad9154_rst_n", 0).eq(1),
platform.request("ad9154_rst_n", 1).eq(1)
]
self.submodules.converter_spi = spi2.SPIMaster(
spi2.SPIInterface(platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
csr_devices.append("converter_spi")
self.comb += platform.request("hmc7043_reset").eq(0)
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 10.)
serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device,
serwb_pads,
mode="slave",
phy_width=4)
self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk)
csr_devices.append("serwb_phy_rtm")
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm,
int(clk_freq),
mode="master",
with_scrambling=True)
self.submodules += serwb_core
# process CSR devices and connect them to serwb
self.csr_regions = []
wb_slaves = WishboneSlaveManager(0x10000000)
for i, name in enumerate(csr_devices):
origin = i * CSR_RANGE_SIZE
module = getattr(self, name)
csrs = module.get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
self.csr_regions.append((name, origin, 32, csrs))
self.submodules += wishbone.Decoder(
serwb_core.etherbone.wishbone.bus,
wb_slaves.get_interconnect_slaves(),
register=True)
