def __init__(self, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
**kwargs)
platform = self.platform
rtio_clk_freq = 150e6
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("si5324_clkout")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p,
i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0)
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9 / rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk,
gtp.rxoutclk)
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
fix_serdes_timing_path(platform)
def __init__(self, rtio_clk_freq=150e6, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
**kwargs)
add_identifier(self)
platform = self.platform
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("si5324_clkout")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(
refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[platform.request("sfp", i) for i in range(3)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.comb += [sfp_ctl.led.eq(channel.rx_ready)
for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)]
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
drtiorep_csr_group = []
self.drtio_cri = []
for i in range(3):
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[i],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
else:
corerep_name = "drtiorep" + str(i-1)
drtiorep_csr_group.append(corerep_name)
core = cdr(DRTIORepeater(
self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.clk125_div2, ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9/rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self,
rtio_clk_freq=125e6,
enable_sata=False,
*,
with_wrpll=False,
gateware_identifier_str=None,
**kwargs):
BaseSoC.__init__(self,
cpu_type="vexriscv",
sdram_controller_type="minicon",
l2_size=128 * 1024,
**kwargs)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
platform = self.platform
disable_cdr_clk_ibuf = Signal(reset=1)
disable_cdr_clk_ibuf.attr.add("no_retiming")
if self.platform.hw_rev == "v2.0":
cdr_clk_clean = self.platform.request("cdr_clk_clean")
else:
cdr_clk_clean = self.platform.request("si5324_clkout")
cdr_clk_clean_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_cdr_clk_ibuf,
i_I=cdr_clk_clean.p,
i_IB=cdr_clk_clean.n,
o_O=cdr_clk_clean_buf)
qpll_drtio_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(cdr_clk_clean_buf, qpll_drtio_settings)
self.submodules += qpll
drtio_data_pads = []
if enable_sata:
drtio_data_pads.append(platform.request("sata"))
drtio_data_pads += [platform.request("sfp", i) for i in range(3)]
if self.platform.hw_rev == "v2.0":
drtio_data_pads.append(platform.request("sfp", 3))
if self.platform.hw_rev in ("v1.0", "v1.1"):
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_cdr_clk_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
if enable_sata:
sfp_channels = self.drtio_transceiver.channels[1:]
else:
sfp_channels = self.drtio_transceiver.channels
if self.platform.hw_rev in ("v1.0", "v1.1"):
self.comb += [
sfp_ctl.led.eq(channel.rx_ready)
for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)
]
if self.platform.hw_rev == "v2.0":
self.comb += [
self.virtual_leds.get(i).eq(channel.rx_ready)
for i, channel in enumerate(sfp_channels)
]
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
drtiorep_csr_group = []
self.drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(
DRTIOSatellite(self.rtio_tsc,
self.drtio_transceiver.channels[i],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
else:
corerep_name = "drtiorep" + str(i - 1)
drtiorep_csr_group.append(corerep_name)
core = cdr(
DRTIORepeater(self.rtio_tsc,
self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
rtio_clk_period = 1e9 / rtio_clk_freq
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
if with_wrpll:
self.submodules.wrpll_sampler = DDMTDSamplerGTP(
self.drtio_transceiver,
platform.request("cdr_clk_clean_fabric"))
helper_clk_pads = platform.request("ddmtd_helper_clk")
self.submodules.wrpll = WRPLL(
helper_clk_pads=helper_clk_pads,
main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
ddmtd_inputs=self.wrpll_sampler)
self.csr_devices.append("wrpll")
# note: do not use self.wrpll.cd_helper.clk; otherwise, vivado craps out with:
# critical warning: create_clock attempting to set clock on an unknown port/pin
# command: "create_clock -period 7.920000 -waveform {0.000000 3.960000} -name
# helper_clk [get_xlnx_outside_genome_inst_pin 20 0]
platform.add_period_constraint(helper_clk_pads.p,
rtio_clk_period * 0.99)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
helper_clk_pads.p)
else:
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("cdr_clk") if platform.hw_rev
== "v2.0" else platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.clk125_div2,
ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk,
gtp.rxoutclk)
if with_wrpll:
platform.add_false_path_constraints(helper_clk_pads.p,
gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
**kwargs)
platform = self.platform
rtio_clk_freq = 150e6
rtio_channels = []
phy = ttl_simple.Output(platform.request("user_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(1, 3):
phy = ttl_simple.Output(platform.request("sfp_ctl", i).led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("si5324_clkout")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(
refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0)
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
self.submodules.drtio0 = rx0(DRTIOSatellite(
self.drtio_transceiver.channels[0], rtio_channels,
self.rx_synchronizer))
self.csr_devices.append("drtio0")
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus)
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
si5324_clkin = platform.request("si5324_clkin")
self.specials += \
Instance("OBUFDS",
i_I=ClockSignal("rtio_rx0"),
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
)
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9/rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
def __init__(self, rtio_clk_freq=150e6, enable_sata=False, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
**kwargs)
add_identifier(self)
platform = self.platform
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("si5324_clkout")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(
refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
drtio_data_pads = []
if enable_sata:
drtio_data_pads.append(platform.request("sata"))
drtio_data_pads += [platform.request("sfp", i) for i in range(3)]
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
if enable_sata:
sfp_channels = self.drtio_transceiver.channels[1:]
else:
sfp_channels = self.drtio_transceiver.channels
self.comb += [sfp_ctl.led.eq(channel.rx_ready)
for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)]
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
drtiorep_csr_group = []
self.drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[i],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
else:
corerep_name = "drtiorep" + str(i-1)
drtiorep_csr_group.append(corerep_name)
core = cdr(DRTIORepeater(
self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.clk125_div2, ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9/rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
**kwargs)
platform = self.platform
rtio_clk_freq = 150e6
rtio_channels = []
phy = ttl_simple.Output(platform.request("user_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.Output(platform.request("sfp_ctl", 1).led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
si5324_clkout = platform.request("si5324_clkout")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=si5324_clkout.p,
i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0)
self.submodules.transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.drtio0 = rx0(
DRTIOSatellite(self.transceiver.channels[0], rtio_channels))
self.csr_devices.append("drtio0")
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus)
self.add_memory_region("drtio0_aux",
self.mem_map["drtio_aux"] | self.shadow_base,
0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
si5324_clkin = platform.request("si5324_clkin")
self.specials += \
Instance("OBUFDS",
i_I=ClockSignal("rtio_rx0"),
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
)
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9 / rtio_clk_freq
gtp = self.transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk,
gtp.rxoutclk)