def __init__(self, platform): GenSoC.__init__(self, platform, clk_freq=80*1000000, cpu_reset_address=0x60000) platform.add_extension(_tester_io) self.submodules.crg = _CRG(platform) # BIOS is in SPI flash self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), cmd=0xefef, cmd_width=16, addr_width=24, dummy=4) self.flash_boot_address = 0x70000 self.register_rom(self.spiflash.bus) # Use block RAM instead of SDRAM for now sys_ram_size = 32*1024 self.submodules.sys_ram = wishbone.SRAM(sys_ram_size) self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus) self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size) self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2))) self.submodules.test_inputs = gpio.GPIOIn(Cat([platform.request("pmt", i) for i in range(3)], platform.request("xtrig"))) self.submodules.test_ttl = ttlgpio.TTLGPIO(platform.request("ttl")) self.submodules.dds = ad9858.AD9858(platform.request("dds")) self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
def __init__(self, platform): GenSoC.__init__(self, platform, clk_freq=80 * 1000000, cpu_reset_address=0x60000) platform.add_extension(_tester_io) self.submodules.crg = _CRG(platform) # BIOS is in SPI flash self.submodules.spiflash = spiflash.SpiFlash( platform.request("spiflash2x"), cmd=0xefef, cmd_width=16, addr_width=24, dummy=4) self.flash_boot_address = 0x70000 self.register_rom(self.spiflash.bus) # Use block RAM instead of SDRAM for now sys_ram_size = 32 * 1024 self.submodules.sys_ram = wishbone.SRAM(sys_ram_size) self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus) self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size) self.submodules.leds = gpio.GPIOOut( Cat(platform.request("user_led", i) for i in range(2))) self.submodules.test_inputs = gpio.GPIOIn(platform.request("inputs")) self.submodules.test_ttl = ttlgpio.TTLGPIO(platform.request("ttl")) self.submodules.dds = ad9858.AD9858(platform.request("dds")) self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
def __init__(self, platform): GenSoC.__init__(self, platform, clk_freq=self.clk_freq, cpu_reset_address=0) IntegratedBIOS.__init__(self) self.submodules.crg = _CRG(platform.request(self.clk_name)) # use on-board SRAM as SDRAM sys_ram_size = 16*1024 self.submodules.sys_ram = wishbone.SRAM(sys_ram_size) self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus) self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)
def __init__(self, platform): GenSoC.__init__(self, platform, clk_freq=32*1000000, cpu_reset_address=0, sram_size=4096) IntegratedBIOS.__init__(self) # We can't use reset_less as LM32 does require a reset signal self.clock_domains.cd_sys = ClockDomain() self.comb += self.cd_sys.clk.eq(platform.request("clk32")) self.specials += Instance("FD", p_INIT=1, i_D=0, o_Q=self.cd_sys.rst, i_C=ClockSignal()) self.submodules.leds = gpio.GPIOOut(platform.request("user_led")) # Map the SPI flash at 0xb0000000 for demo purposes. Later, we'll want to store the BIOS there. self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), cmd=0xefef, cmd_width=16, addr_width=24, dummy=4) self.add_wb_slave(lambda a: a[26:29] == 3, self.spiflash.bus)
def __init__(self, platform): GenSoC.__init__(self, platform, clk_freq=32*1000000, cpu_reset_address=0x60000) # We can't use reset_less as LM32 does require a reset signal self.clock_domains.cd_sys = ClockDomain() self.submodules += PowerOnRst(self.cd_sys) self.comb += self.cd_sys.clk.eq(platform.request("clk32")) # BIOS is in SPI flash self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), cmd=0xefef, cmd_width=16, addr_width=24, dummy=4) self.flash_boot_address = 0x70000 self.register_rom(self.spiflash.bus) # TODO: use on-board SDRAM instead of block RAM sys_ram_size = 32*1024 self.submodules.sys_ram = wishbone.SRAM(sys_ram_size) self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus) self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)