Пример #1
0
 def __init__(self, platform, **kwargs):
     SoC.__init__(self, platform,
                  clk_freq=100*1000000,
                  integrated_rom_size=0x8000,
                  **kwargs)
     self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
     self.comb += platform.request("user_led", 0).eq(ResetSignal())
Пример #2
0
    def __init__(self, platform):
        clk_freq = int((1/(platform.default_clk_period))*1000000000)
        SoC.__init__(self, platform, clk_freq,
            cpu_type="none",
            with_csr=True, csr_data_width=32,
            with_uart=False,
            with_identifier=True,
            with_timer=False
        )
        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
        self.add_wb_master(self.cpu_or_bridge.wishbone)
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        self.submodules.io = LiteScopeIO(8)
        for i in range(8):
            try:
                self.comb += platform.request("user_led", i).eq(self.io.o[i])
            except:
                pass

        self.submodules.counter0 = counter0 = Counter(8)
        self.submodules.counter1 = counter1 = Counter(8)
        self.comb += [
            counter0.ce.eq(1),
            If(counter0.value == 16,
                counter0.reset.eq(1),
                counter1.ce.eq(1)
            )
        ]

        self.debug = (
            counter1.value
        )
        self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True)
        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
Пример #3
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    def __init__(self, platform):
        clk_freq = 200*1000000
        SoC.__init__(self, platform, clk_freq,
            cpu_type="none",
            with_csr=True, csr_data_width=32,
            with_uart=False,
            with_identifier=True,
            with_timer=False
        )
        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
        self.add_wb_master(self.cpu_or_bridge.wishbone)
        self.submodules.crg = CRG(platform)

        # SATA PHY/Core/Frontend
        self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq)
        self.submodules.sata_core = LiteSATACore(self.sata_phy)
        self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
        self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)

        # Status Leds
        self.submodules.leds = StatusLeds(platform, self.sata_phy)

        platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]

create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]

set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""")
Пример #4
0
    def __init__(self, platform):
        clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
        SoC.__init__(self,
                     platform,
                     clk_freq,
                     cpu_type="none",
                     with_csr=True,
                     csr_data_width=32,
                     with_uart=False,
                     with_identifier=True,
                     with_timer=False)
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"),
                                           self.clk_freq)
        self.submodules.usb_core = LiteUSBCore(self.usb_phy,
                                               self.clk_freq,
                                               with_crc=False)

        # Wishbone Bridge
        usb_bridge_port = self.usb_core.crossbar.get_port(
            self.usb_map["bridge"])
        self.add_cpu_or_bridge(
            LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq))
        self.add_wb_master(self.cpu_or_bridge.wishbone)

        # Leds
        leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
        self.submodules.leds = GPIOOut(leds)
Пример #5
0
 def __init__(self, platform, **kwargs):
     SoC.__init__(self,
                  platform,
                  clk_freq=int(
                      (1 / (platform.default_clk_period)) * 1000000000),
                  integrated_rom_size=0x8000,
                  integrated_main_ram_size=16 * 1024,
                  **kwargs)
     self.submodules.crg = CRG(platform.request(platform.default_clk_name))
Пример #6
0
    def __init__(self, platform):
        clk_freq = 200*1000000
        SoC.__init__(self, platform, clk_freq,
            cpu_type="none",
            with_csr=True, csr_data_width=32,
            with_uart=False,
            with_identifier=True,
            with_timer=False
        )
        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
        self.add_wb_master(self.cpu_or_bridge.wishbone)
        self.submodules.crg = CRG(platform)

        # SATA PHYs
        sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq)
        sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen3", clk_freq)
        sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen3", clk_freq)
        sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen3", clk_freq)
        sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3]
        for i, sata_phy in enumerate(sata_phys):
            sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)),
                                                     "sata_tx": "sata_tx{}".format(str(i))})
            setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)

        # SATA Cores
        self.submodules.sata_core0 = LiteSATACore(self.sata_phy0)
        self.submodules.sata_core1 = LiteSATACore(self.sata_phy1)
        self.submodules.sata_core2 = LiteSATACore(self.sata_phy2)
        self.submodules.sata_core3 = LiteSATACore(self.sata_phy3)
        sata_cores = [self.sata_core0, self.sata_core1, self.sata_core2, self.sata_core3]

        # SATA Frontend
        self.submodules.sata_striping = LiteSATAStriping(sata_cores)
        self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_striping)

        # SATA Application
        self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)

        # Status Leds
        self.submodules.status_leds = StatusLeds(platform, sata_phys)


        platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
""")

        for i in range(len(sata_phys)):
            platform.add_platform_command("""
create_clock -name {sata_rx_clk} -period 3.33 [get_nets {sata_rx_clk}]
create_clock -name {sata_tx_clk} -period 3.33 [get_nets {sata_tx_clk}]

set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
           sata_tx_clk="sata_tx{}_clk".format(str(i))))
Пример #7
0
 def __init__(self, platform, **kwargs):
     SoC.__init__(self,
                  platform,
                  clk_freq=100 * 1000000,
                  integrated_rom_size=0x8000,
                  **kwargs)
     self.submodules.crg = CRG(platform.request("clk100"),
                               ~platform.request("rst_n"))
     self.comb += platform.request("user_led", 0).eq(ResetSignal())
Пример #8
0
 def __init__(self, platform, **kwargs):
     SoC.__init__(
         self,
         platform,
         clk_freq=int((1 / (platform.default_clk_period)) * 1000000000),
         integrated_rom_size=0x8000,
         integrated_main_ram_size=16 * 1024,
         **kwargs
     )
     self.submodules.crg = CRG(platform.request(platform.default_clk_name))
Пример #9
0
 def __init__(self, platform, clk_freq, sdram_controller_settings,
              **kwargs):
     SoC.__init__(self, platform, clk_freq, **kwargs)
     if isinstance(sdram_controller_settings, str):
         self.sdram_controller_settings = eval(sdram_controller_settings)
     else:
         self.sdram_controller_settings = sdram_controller_settings
     self._sdram_phy_registered = False
     self._wb_sdram_ifs = []
     self._wb_sdram = wishbone.Interface()
Пример #10
0
    def do_finalize(self):
        if not self.integrated_main_ram_size:
            if not self._sdram_phy_registered:
                raise FinalizeError(
                    "Need to call SDRAMSoC.register_sdram_phy()")

            # arbitrate wishbone interfaces to the DRAM
            self.submodules.wb_sdram_con = wishbone.Arbiter(
                self._wb_sdram_ifs, self._wb_sdram)
        SoC.do_finalize(self)
Пример #11
0
    def __init__(self,
                 platform,
                 clk_freq=166 * 1000000,
                 mac_address=0x10e2d5000000,
                 ip_address="192.168.0.42"):
        clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
        SoC.__init__(self,
                     platform,
                     clk_freq,
                     cpu_type="none",
                     with_csr=True,
                     csr_data_width=32,
                     with_uart=False,
                     with_identifier=True,
                     with_timer=False)
        self.add_cpu_or_bridge(
            UARTWishboneBridge(platform.request("serial"),
                               clk_freq,
                               baudrate=115200))
        self.add_wb_master(self.cpu_or_bridge.wishbone)
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        # wishbone SRAM (to test Wishbone over UART and Etherbone)
        self.submodules.sram = wishbone.SRAM(1024)
        self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)

        # ethernet PHY and UDP/IP stack
        self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"),
                                         platform.request("eth"),
                                         clk_freq=clk_freq)
        self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address,
                                                convert_ip(ip_address),
                                                clk_freq)

        if isinstance(platform.toolchain, XilinxVivadoToolchain):
            self.specials += [
                Keep(self.crg.cd_sys.clk),
                Keep(self.phy.crg.cd_eth_rx.clk),
                Keep(self.phy.crg.cd_eth_tx.clk)
            ]
            platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
""")
Пример #12
0
    def __init__(self, platform, with_uart_bridge=True):
        clk_freq = 125 * 1000000
        SoC.__init__(self,
                     platform,
                     clk_freq,
                     cpu_type="none",
                     shadow_base=0x00000000,
                     with_csr=True,
                     csr_data_width=32,
                     with_uart=False,
                     with_identifier=True,
                     with_timer=False)
        self.submodules.crg = _CRG(platform)

        # PCIe endpoint
        self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)
        self.submodules.pcie_endpoint = Endpoint(self.pcie_phy,
                                                 with_reordering=True)

        # PCIe Wishbone bridge
        self.add_cpu_or_bridge(
            LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1))
        self.add_wb_master(self.cpu_or_bridge.wishbone)

        # PCIe DMA
        self.submodules.dma = DMA(self.pcie_phy,
                                  self.pcie_endpoint,
                                  with_loopback=True)
        self.dma.source.connect(self.dma.sink)

        if with_uart_bridge:
            self.submodules.uart_bridge = UARTWishboneBridge(
                platform.request("serial"), clk_freq, baudrate=115200)
            self.add_wb_master(self.uart_bridge.wishbone)

        # IRQs
        self.submodules.irq_controller = InterruptController()
        self.comb += self.irq_controller.source.connect(
            self.pcie_phy.interrupt)
        self.interrupts = {
            "dma_writer": self.dma.writer.table.irq,
            "dma_reader": self.dma.reader.table.irq
        }
        for k, v in sorted(self.interrupts.items()):
            self.comb += self.irq_controller.irqs[self.interrupt_map[k]].eq(v)
Пример #13
0
    def __init__(self, platform):
        clk_freq = 200 * 1000000
        SoC.__init__(
            self,
            platform,
            clk_freq,
            cpu_type="none",
            with_csr=True,
            csr_data_width=32,
            with_uart=False,
            with_identifier=True,
            with_timer=False,
        )
        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
        self.add_wb_master(self.cpu_or_bridge.wishbone)
        self.submodules.crg = CRG(platform)

        # SATA PHY/Core/Frontend
        self.submodules.sata_phy = LiteSATAPHY(
            platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen3", clk_freq
        )
        self.submodules.sata_core = LiteSATACore(self.sata_phy)
        self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
        self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)

        # Status Leds
        self.submodules.leds = StatusLeds(platform, self.sata_phy)

        platform.add_platform_command(
            """
create_clock -name sys_clk -period 5 [get_nets sys_clk]

create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]

set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
"""
        )
Пример #14
0
    def __init__(self, platform, clk_freq=166*1000000,
            mac_address=0x10e2d5000000,
            ip_address="192.168.0.42"):
        clk_freq = int((1/(platform.default_clk_period))*1000000000)
        SoC.__init__(self, platform, clk_freq,
            cpu_type="none",
            with_csr=True, csr_data_width=32,
            with_uart=False,
            with_identifier=True,
            with_timer=False
        )
        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
        self.add_wb_master(self.cpu_or_bridge.wishbone)
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        # wishbone SRAM (to test Wishbone over UART and Etherbone)
        self.submodules.sram = wishbone.SRAM(1024)
        self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)

        # ethernet PHY and UDP/IP stack
        self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq)
        self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)

        if isinstance(platform.toolchain, XilinxVivadoToolchain):
            self.specials += [
                Keep(self.crg.cd_sys.clk),
                Keep(self.phy.crg.cd_eth_rx.clk),
                Keep(self.phy.crg.cd_eth_tx.clk)
            ]
            platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
""")
Пример #15
0
    def __init__(self, platform):
        clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
        SoC.__init__(self,
                     platform,
                     clk_freq,
                     cpu_type="none",
                     with_csr=True,
                     csr_data_width=32,
                     with_uart=False,
                     with_identifier=True,
                     with_timer=False)
        self.add_cpu_or_bridge(
            UARTWishboneBridge(platform.request("serial"),
                               clk_freq,
                               baudrate=115200))
        self.add_wb_master(self.cpu_or_bridge.wishbone)
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        self.submodules.io = LiteScopeIO(8)
        for i in range(8):
            try:
                self.comb += platform.request("user_led", i).eq(self.io.o[i])
            except:
                pass

        self.submodules.counter0 = counter0 = Counter(8)
        self.submodules.counter1 = counter1 = Counter(8)
        self.comb += [
            counter0.ce.eq(1),
            If(counter0.value == 16, counter0.reset.eq(1), counter1.ce.eq(1))
        ]

        self.debug = (counter1.value)
        self.submodules.la = LiteScopeLA(self.debug,
                                         512,
                                         with_rle=True,
                                         with_subsampler=True)
        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
Пример #16
0
    def __init__(self, platform):
        clk_freq = int((1/(platform.default_clk_period))*1000000000)
        SoC.__init__(self, platform, clk_freq,
            cpu_type="none",
            with_csr=True, csr_data_width=32,
            with_uart=False,
            with_identifier=True,
            with_timer=False
        )
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
        self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)


        # Wishbone Bridge
        usb_bridge_port = self.usb_core.crossbar.get_port(self.usb_map["bridge"])
        self.add_cpu_or_bridge(LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq))
        self.add_wb_master(self.cpu_or_bridge.wishbone)

        # Leds
        leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
        self.submodules.leds = GPIOOut(leds)
Пример #17
0
Файл: dma.py Проект: olofk/misoc
    def __init__(self, platform, with_uart_bridge=True):
        clk_freq = 125*1000000
        SoC.__init__(self, platform, clk_freq,
            cpu_type="none",
            shadow_base=0x00000000,
            with_csr=True, csr_data_width=32,
            with_uart=False,
            with_identifier=True,
            with_timer=False
        )
        self.submodules.crg = _CRG(platform)

        # PCIe endpoint
        self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)
        self.submodules.pcie_endpoint = Endpoint(self.pcie_phy, with_reordering=True)

        # PCIe Wishbone bridge
        self.add_cpu_or_bridge(LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1))
        self.add_wb_master(self.cpu_or_bridge.wishbone)

        # PCIe DMA
        self.submodules.dma = DMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
        self.dma.source.connect(self.dma.sink)

        if with_uart_bridge:
            self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
            self.add_wb_master(self.uart_bridge.wishbone)

        # IRQs
        self.submodules.irq_controller = InterruptController()
        self.comb += self.irq_controller.source.connect(self.pcie_phy.interrupt)
        self.interrupts = {
            "dma_writer":    self.dma.writer.table.irq,
            "dma_reader":    self.dma.reader.table.irq
        }
        for k, v in sorted(self.interrupts.items()):
            self.comb += self.irq_controller.irqs[self.interrupt_map[k]].eq(v)