Пример #1
0
    def __init__(self, platform):
        BaseSoC.__init__(self, platform)

        self.core_icmp_rx_fsm_state = Signal(4)
        self.core_icmp_tx_fsm_state = Signal(4)
        self.core_udp_rx_fsm_state = Signal(4)
        self.core_udp_tx_fsm_state = Signal(4)
        self.core_ip_rx_fsm_state = Signal(4)
        self.core_ip_tx_fsm_state = Signal(4)
        self.core_arp_rx_fsm_state = Signal(4)
        self.core_arp_tx_fsm_state = Signal(4)
        self.core_arp_table_fsm_state = Signal(4)

        debug = (
            # MAC interface
            self.core.mac.core.sink.stb,
            self.core.mac.core.sink.sop,
            self.core.mac.core.sink.eop,
            self.core.mac.core.sink.ack,
            self.core.mac.core.sink.data,
            self.core.mac.core.source.stb,
            self.core.mac.core.source.sop,
            self.core.mac.core.source.eop,
            self.core.mac.core.source.ack,
            self.core.mac.core.source.data,

            # ICMP interface
            self.core.icmp.echo.sink.stb,
            self.core.icmp.echo.sink.sop,
            self.core.icmp.echo.sink.eop,
            self.core.icmp.echo.sink.ack,
            self.core.icmp.echo.sink.data,
            self.core.icmp.echo.source.stb,
            self.core.icmp.echo.source.sop,
            self.core.icmp.echo.source.eop,
            self.core.icmp.echo.source.ack,
            self.core.icmp.echo.source.data,

            # IP interface
            self.core.ip.crossbar.master.sink.stb,
            self.core.ip.crossbar.master.sink.sop,
            self.core.ip.crossbar.master.sink.eop,
            self.core.ip.crossbar.master.sink.ack,
            self.core.ip.crossbar.master.sink.data,
            self.core.ip.crossbar.master.sink.ip_address,
            self.core.ip.crossbar.master.sink.protocol,

            # State machines
            self.core_icmp_rx_fsm_state,
            self.core_icmp_tx_fsm_state,
            self.core_arp_rx_fsm_state,
            self.core_arp_tx_fsm_state,
            self.core_arp_table_fsm_state,
            self.core_ip_rx_fsm_state,
            self.core_ip_tx_fsm_state,
            self.core_udp_rx_fsm_state,
            self.core_udp_tx_fsm_state)
        self.submodules.la = LiteScopeLA(debug, 4096)
        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
Пример #2
0
    def __init__(self, platform):
        TTYSoC.__init__(self, platform)
        debug = (
            self.tty.sink.stb,
            self.tty.sink.ack,
            self.tty.sink.data,

            self.tty.source.stb,
            self.tty.source.ack,
            self.tty.source.data
        )
        self.submodules.la = LiteScopeLA(debug, 4096)
        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
Пример #3
0
 def __init__(self, platform):
     UDPSoC.__init__(self, platform)
     debug = (self.loopback_8.sink.stb, self.loopback_8.sink.sop,
              self.loopback_8.sink.eop, self.loopback_8.sink.ack,
              self.loopback_8.sink.data, self.loopback_8.source.stb,
              self.loopback_8.source.sop, self.loopback_8.source.eop,
              self.loopback_8.source.ack, self.loopback_8.source.data,
              self.loopback_32.sink.stb, self.loopback_32.sink.sop,
              self.loopback_32.sink.eop, self.loopback_32.sink.ack,
              self.loopback_32.sink.data, self.loopback_32.source.stb,
              self.loopback_32.source.sop, self.loopback_32.source.eop,
              self.loopback_32.source.ack, self.loopback_32.source.data)
     self.submodules.la = LiteScopeLA(debug, 4096)
     self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
Пример #4
0
    def __init__(self, platform):
        BISTSoC.__init__(self, platform)

        self.sata_core_link_rx_fsm_state = Signal(4)
        self.sata_core_link_tx_fsm_state = Signal(4)
        self.sata_core_transport_rx_fsm_state = Signal(4)
        self.sata_core_transport_tx_fsm_state = Signal(4)
        self.sata_core_command_rx_fsm_state = Signal(4)
        self.sata_core_command_tx_fsm_state = Signal(4)

        debug = (
            self.sata_phy.ctrl.ready,

            self.sata_phy.source.stb,
            self.sata_phy.source.data,
            self.sata_phy.source.charisk,

            self.sata_phy.sink.stb,
            self.sata_phy.sink.data,
            self.sata_phy.sink.charisk,

            self.sata.core.command.sink.stb,
            self.sata.core.command.sink.sop,
            self.sata.core.command.sink.eop,
            self.sata.core.command.sink.ack,
            self.sata.core.command.sink.write,
            self.sata.core.command.sink.read,
            self.sata.core.command.sink.identify,

            self.sata.core.command.source.stb,
            self.sata.core.command.source.sop,
            self.sata.core.command.source.eop,
            self.sata.core.command.source.ack,
            self.sata.core.command.source.write,
            self.sata.core.command.source.read,
            self.sata.core.command.source.identify,
            self.sata.core.command.source.failed,
            self.sata.core.command.source.data,

            self.sata_core_link_rx_fsm_state,
            self.sata_core_link_tx_fsm_state,
            self.sata_core_transport_rx_fsm_state,
            self.sata_core_transport_tx_fsm_state,
            self.sata_core_command_rx_fsm_state,
            self.sata_core_command_tx_fsm_state,
        )

        self.submodules.la = LiteScopeLA(debug, 2048)
        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
Пример #5
0
    def __init__(self, platform):
        EtherboneSoC.__init__(self, platform)
        debug = (
            # mmap stream from HOST
            self.etherbone.master.sink.stb,
            self.etherbone.master.sink.sop,
            self.etherbone.master.sink.eop,
            self.etherbone.master.sink.ack,
            self.etherbone.master.sink.we,
            self.etherbone.master.sink.count,
            self.etherbone.master.sink.base_addr,
            self.etherbone.master.sink.be,
            self.etherbone.master.sink.addr,
            self.etherbone.master.sink.data,

            # mmap stream to HOST
            self.etherbone.master.source.stb,
            self.etherbone.master.source.sop,
            self.etherbone.master.source.eop,
            self.etherbone.master.source.ack,
            self.etherbone.master.source.we,
            self.etherbone.master.source.count,
            self.etherbone.master.source.base_addr,
            self.etherbone.master.source.be,
            self.etherbone.master.source.addr,
            self.etherbone.master.source.data,

            # etherbone wishbone master
            self.etherbone.master.bus.dat_w,
            self.etherbone.master.bus.dat_r,
            self.etherbone.master.bus.adr,
            self.etherbone.master.bus.sel,
            self.etherbone.master.bus.cyc,
            self.etherbone.master.bus.stb,
            self.etherbone.master.bus.ack,
            self.etherbone.master.bus.we,
            self.etherbone.master.bus.cti,
            self.etherbone.master.bus.bte,
            self.etherbone.master.bus.err
        )
        self.submodules.la = LiteScopeLA(debug, 4096)
        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
Пример #6
0
    def __init__(self, platform):
        clk_freq = int((1 / (platform.default_clk_period)) * 1000000000)
        SoC.__init__(self,
                     platform,
                     clk_freq,
                     cpu_type="none",
                     with_csr=True,
                     csr_data_width=32,
                     with_uart=False,
                     with_identifier=True,
                     with_timer=False)
        self.add_cpu_or_bridge(
            UARTWishboneBridge(platform.request("serial"),
                               clk_freq,
                               baudrate=115200))
        self.add_wb_master(self.cpu_or_bridge.wishbone)
        self.submodules.crg = CRG(platform.request(platform.default_clk_name))

        self.submodules.io = LiteScopeIO(8)
        for i in range(8):
            try:
                self.comb += platform.request("user_led", i).eq(self.io.o[i])
            except:
                pass

        self.submodules.counter0 = counter0 = Counter(8)
        self.submodules.counter1 = counter1 = Counter(8)
        self.comb += [
            counter0.ce.eq(1),
            If(counter0.value == 16, counter0.reset.eq(1), counter1.ce.eq(1))
        ]

        self.debug = (counter1.value)
        self.submodules.la = LiteScopeLA(self.debug,
                                         512,
                                         with_rle=True,
                                         with_subsampler=True)
        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
Пример #7
0
    def __init__(self, platform):
        StripingSoC.__init__(self, platform)

        self.sata_core0_link_tx_fsm_state = Signal(4)
        self.sata_core0_link_rx_fsm_state = Signal(4)

        self.sata_core1_link_tx_fsm_state = Signal(4)
        self.sata_core1_link_rx_fsm_state = Signal(4)

        self.sata_core2_link_tx_fsm_state = Signal(4)
        self.sata_core2_link_rx_fsm_state = Signal(4)

        self.sata_core3_link_tx_fsm_state = Signal(4)
        self.sata_core3_link_rx_fsm_state = Signal(4)

        debug = (
            self.sata_phy0.ctrl.ready,
            self.sata_phy1.ctrl.ready,
            self.sata_phy2.ctrl.ready,
            self.sata_phy3.ctrl.ready,

            self.sata_core0_link_tx_fsm_state,
            self.sata_core0_link_rx_fsm_state,

            self.sata_core0.sink.stb,
            self.sata_core0.source.stb,

            self.sata_phy0.source.stb,
            self.sata_phy0.source.data,
            self.sata_phy0.source.charisk,

            self.sata_phy0.sink.stb,
            self.sata_phy0.sink.data,
            self.sata_phy0.sink.charisk,

            self.sata_core1_link_tx_fsm_state,
            self.sata_core1_link_rx_fsm_state,

            self.sata_core1.sink.stb,
            self.sata_core1.source.stb,

            self.sata_phy1.source.stb,
            self.sata_phy1.source.data,
            self.sata_phy1.source.charisk,

            self.sata_phy1.sink.stb,
            self.sata_phy1.sink.data,
            self.sata_phy1.sink.charisk,

            self.sata_core2_link_tx_fsm_state,
            self.sata_core2_link_rx_fsm_state,

            self.sata_core2.sink.stb,
            self.sata_core2.source.stb,

            self.sata_phy2.source.stb,
            self.sata_phy2.source.data,
            self.sata_phy2.source.charisk,

            self.sata_phy2.sink.stb,
            self.sata_phy2.sink.data,
            self.sata_phy2.sink.charisk,

            self.sata_core3_link_tx_fsm_state,
            self.sata_core3_link_rx_fsm_state,

            self.sata_core3.sink.stb,
            self.sata_core3.source.stb,

            self.sata_phy3.source.stb,
            self.sata_phy3.source.data,
            self.sata_phy3.source.charisk,

            self.sata_phy3.sink.stb,
            self.sata_phy3.sink.data,
            self.sata_phy3.sink.charisk
        )

        self.submodules.la = LiteScopeLA(debug, 2048)
        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))