def orderHardAssigns(Mod,Env):
HAS = {}
Ordered=[]
Ins = []
Regs = []
for Net in Mod.nets:
Dir,_ = Mod.nets[Net]
if 'input' in Dir: Ins.append(Net)
if 'reg' in Dir: Regs.append(Net)
for ind,(Dst,Src,_,_) in enumerate(Mod.hard_assigns):
if Dst!='//':
Sup0 = support_set(Dst,False)
Sup1 = support_set(Src,False)
HAS[ind]=(Sup0,Sup1)
ReadyList = Ins[:]+Regs[:]
WorkList = HAS.keys()
while len(WorkList)!=0:
pos=0
while pos<len(WorkList):
ind = WorkList[pos]
Dst,Src = HAS[ind]
if allReady(Src,ReadyList):
WorkList.pop(pos)
pos=999999
ReadyList.extend(Dst)
Ordered.append(ind)
def scanBody(Body, Conds, Path):
if (type(Body) is tuple) or (type(Body) is list):
if Body[0] in ['=', '<=']:
Dsts = support_set(Body[1], False)
Srcs = support_set(Body[2], False)
for S in Srcs + Conds:
for D in Dsts:
recordTable(Path + '.' + S, Path + '.' + D)
return
if Body[0] == 'list':
for Item in Body[1:]:
scanBody(Item, Conds, Path)
return
if Body[0] == 'ifelse':
More = support_set(Body[1], False)
scanBody(Body[2], Conds + More, Path)
scanBody(Body[3], Conds + More, Path)
return
if Body[0] == 'if':
More = support_set(Body[1], False)
scanBody(Body[2], Conds + More, Path)
return
if Body[0] == 'case':
More = support_set(Body[1], False)
for Label, Item in Body[2]:
scanBody(Item, Conds + More, Path)
return
logs.log_error('scanBody failed on %s' % str(Body[0]))
return
def blobify(Mod):
Blobs = []
for (Dst, Src, _, _) in Mod.hard_assigns:
Sups = module_class.support_set(Src)
Supd = module_class.support_set(Dst)
Blobs.append((Supd, Sups, Dst, Src))
return Blobs
def undefinedWires(Mod):
Sets = []
Founds = {}
for Inst in Mod.insts:
Obj = Mod.insts[Inst]
for Pin in Obj.conns:
Conn = Obj.conns[Pin]
Set = module_class.support_set(Conn)
Sets.extend(Set)
for Dst, Src, _, _ in Mod.hard_assigns:
Set0 = module_class.support_set(Dst)
Set1 = module_class.support_set(Src)
Sets.extend(Set0)
Sets.extend(Set1)
for Item in Sets:
if type(Item) == types.StringType:
if '[' in Item:
x = Item.index('[')
Bus = Item[:x]
AA = Item[x + 1:]
if ':' in AA:
x = AA.index(':')
Ind = int(AA[:x])
else:
Ind = int(AA[:-1])
if Bus not in Mod.nets:
Founds[Item] = max(Ind, Founds[Item])
elif Item not in Mod.nets:
Founds[Item] = 0
else:
print 'strange %s' % str(Item)
for Bus in Founds:
print Bus, Founds[Bus]
def fixingModule(Mod,Env):
Defs={}
for (Dst,Src,_,_) in Mod.hard_assigns:
Sup0 = support_set(Dst,True)
Sup1 = support_set(Src,True)
for Item in Sup0+Sup1:
if Item not in Mod.parameters:
useForDefs(Item,Defs)
for (Body,When,_) in Mod.alwayses:
Sup0 = support_set(Body,True)
Sup1 = support_set(When,True)
for Item in Sup0+Sup1:
if Item not in Mod.parameters:
useForDefs(Item,Defs)
for Inst in Mod.insts:
Obj = Mod.insts[Inst]
for Pin in Obj.conns:
Sig = Obj.conns[Pin]
Sup0 = support_set(Sig,True)
for Item in Sup0:
if Item not in Mod.parameters:
useForDefs(Item,Defs)
print '>>>',Mod.Module
for Net in Defs:
if Net not in Mod.nets:
print 'net %s is not a net %s'%(Net,Defs[Net])
print 'wire %s %s;\n'%(pr_wid(Wid),pr_expr(Net))
else:
Dir,Wid = Mod.nets[Net]
print 'net %s here=%s mod=%s %s'%(Net,Defs[Net],Dir,Wid)
def scanForRegs(Struct):
Regs = []
if (type(Struct) == types.ListType) and (len(Struct) == 1):
return scanForRegs(Struct[0])
if Struct == []: return []
if complexType(Struct) and (Struct[0] in ['<=', '=']):
Nets = module_class.support_set(Struct[1], False)
for Net in Nets:
if Net not in Regs: Regs.append(Net)
return Regs
if (type(Struct) == types.ListType) and (Struct[0] == 'list'):
for Item in Struct:
More = scanForRegs(Item)
for Net in More:
if Net not in Regs: Regs.append(Net)
return Regs
if complexType(Struct):
if (Struct[0] in [
'assigns', 'genvar', 'comment', 'declare', '<', 'instance'
]):
return []
if (Struct[0] == 'if'):
return scanForRegs(Struct[2])
if (Struct[0] == 'always'):
return scanForRegs(Struct[2])
if (Struct[0] == 'ifelse'):
More = scanForRegs(Struct[2]) + scanForRegs(Struct[3])
for Net in More:
if Net not in Regs: Regs.append(Net)
return Regs
if (Struct[0] in ['unique_case', 'case']):
Struct[0] = 'case'
LL = Struct[2]
for Case in LL:
PP = Case[1]
More = scanForRegs(PP)
for Net in More:
if Net not in Regs: Regs.append(Net)
return Regs
if (Struct[0] == 'taskcall'): return []
if (Struct[0] == 'for'):
Rs = module_class.support_set(Struct[1][1], False)
More = scanForRegs(Struct[4])
return Rs + More
if (Struct[0] == 'named_begin'):
return scanForRegs(Struct[2])
logs.log_error('scanForRegs encountered "%s"' % str(Struct))
logs.pStack()
if type(Struct) in [types.StringType, types.IntType]: return []
logs.log_error('scanForRegs encountered "%s"' % str(Struct))
return Regs
def scanForWires(Mod, Partial=False):
Wires = []
if not Partial:
for Dst, _, _, _ in Mod.hard_assigns:
Nets = module_class.support_set(Dst, False)
for Net in Nets:
if Net not in Wires: Wires.append(Net)
for Gene in Mod.generates:
if Gene[0] in ['if', 'ifelse', 'for']:
More = scanForWires(Mod, Gene)
for Mo in More:
if Mo not in Wires: Wires.append(Mo)
else:
for Item in Gene:
More = scanForWires(Mod, Item)
for Mo in More:
if Mo not in Wires: Wires.append(Mo)
return Wires
if Partial[0] in ['if']:
More = scanForWires(Mod, Partial[2])
return More
if Partial[0] in ['ifelse']:
More = scanForWires(Mod, Partial[2])
More1 = scanForWires(Mod, Partial[3])
for M in More1:
if M not in More:
More.append(M)
return More
if Partial[0] in ['for']:
More = scanForWires(Mod, Partial[4])
return More
if Partial[0] in ['named_begin']:
More = scanForWires(Mod, Partial[2])
return More
if Partial[0] in ['always']: return []
if Partial[0] in ['list']:
Wires = []
for Item in Partial[1:]:
More = scanForWires(Mod, Item)
for Mo in More:
if Mo not in Wires: Wires.append(Mo)
return Wires
if Partial[0] in ['assigns']:
return module_class.support_set(Partial[1][1], False)
if Partial[0] in ['declare']:
return []
logs.log_error('partial %s not recognized' % (str(Partial[0])))
return []
def adds(Dst,Src,Nons):
SetS = support_set(Src,False)
SetD = support_set(Dst,False)
SetS = cleanNons(SetS,Nons+SetD)
for Out in SetD:
if Out not in ARCSBK:
ARCSBK[Out] = []
for In in SetS:
if In not in ARCSBK[Out]: ARCSBK[Out].append(In)
for In in SetS:
if In not in ARCSFW:
ARCSFW[In] = []
for Out in SetD:
if Out not in ARCSFW[In]: ARCSFW[In].append(Out)
def builds(Mod):
Params = []
for Param in Mod.parameters:
Params.append(Param)
for Param in Mod.localparams:
Params.append(Param)
for Dst,Src,_,_ in Mod.hard_assigns:
adds(Dst,Src,Params)
for Inst in Mod.insts:
Obj = Mod.insts[Inst]
SONS.append((Inst,Obj.Type))
for Pin in Obj.conns:
Sig = Obj.conns[Pin]
SetS = support_set(Sig,False)
for Src in SetS:
CONNS.append((Inst,Pin,Src))
for _,Alw,_ in Mod.alwayses:
travelAlw(Alw,[],Params)
for Net in Mod.nets:
Dir,_ = Mod.nets[Net]
if 'output' in Dir: OUTPUTS.append(Net)
if 'input' in Dir: INPUTS.append(Net)
def help_main(Env):
Mod = Env.Current
for Dst, Src, _, _ in Mod.hard_assigns:
Set = module_class.support_set(Src)
logs.log_info('%s <- %s' % (Dst, Set))
for Net in Mod.nets:
Dir, Wid = Mod.nets[Net]
logs.log_info('net %s --- dir=%s wid=%s' % (Net, Dir, Wid))
for Always in Mod.alwayses:
logs.log_info('always %s' % str(Always))
for Inst in Mod.insts:
Obj = Mod.insts[Inst]
logs.log_info('inst=%s kind=%s pins=%s' %
(Inst, Obj.Type, Obj.conns.keys()))
if Mod.functions.keys() == []:
logs.log_info('no functions defined')
if Mod.tasks.keys() == []:
logs.log_info('no tasks defined')
if Mod.generates == []:
logs.log_info('no generates defined')
# functions generates tasks
Dir = dir(Mod)
for Item in Dir:
print Item, type(eval('Mod.%s' % Item))
def parameters(Mod):
Params = []
for Net in Mod.nets:
_,Wid = Mod.nets[Net]
if (type(Wid) is tuple)and(Wid[0] in ['double','triple']):
Sup = module_class.support_set(Wid[1:])
else:
Sup = module_class.support_set(Wid)
if Sup != []:
for Sp in Sup:
if Sp not in Params:
Params.append(Sp)
Params.sort()
if Params!=[]:
logs.log_info('TELL params %s'%str(Params))
for Prm in Params:
if Prm not in Mod.parameters:
if Prm not in Mod.localparams:
Mod.parameters[Prm]=10
def gatherAlwayses(Mod):
for Cond, Body, Kind in Mod.alwayses:
if Cond not in ALWAYS: ALWAYS[Cond] = []
ALWAYS[Cond].append(Body)
Mod.alwayses = []
for Cond in ALWAYS:
logs.log_info('ALWAYS %d %s' % (len(ALWAYS[Cond]), Cond))
List = ALWAYS[Cond]
RList = ['list']
BList = ['list']
if (Cond[0] == 'list'):
for Item in List:
RR = Item[2]
BB = Item[3]
RList.append(RR)
BList.append(BB)
if (BB[0] == '<='):
LL = BB[2]
if (type(LL) is list): LL = tuple(LL)
if LL not in SOURCES: SOURCES.append(LL)
MM = module_class.support_set(Item[1])
for M1 in MM:
if (M1 not in SOURCES): SOURCES.append(M1)
Mod.alwayses.append(
(Cond, ('ifelse', Item[1], RList, BList), 'always'))
elif (Cond[0] == 'edge'):
for Item in List:
BB = Item
BList.append(BB)
if (BB[0] == '<='):
LL = BB[2]
if (type(LL) is list): LL = tuple(LL)
if LL not in SOURCES: SOURCES.append(LL)
MM = module_class.support_set(Item[1])
for M1 in MM:
if (M1 not in SOURCES): SOURCES.append(M1)
Mod.alwayses.append((Cond, BList, 'always'))
else:
logs.log_error('condition list is "%s"' % str(List))
def drive_assist2(Current, Item, Params, Stack):
Sofar = Params[0]
if not Item:
return
if Item[0] == '<=':
Dsts = extract_sigs(Item[1])
Srcs = extract_sigs(Item[2])
for Dst in Dsts:
Stcks = support_set(Stack)
for Src in Srcs + Stcks:
add_edged_drives(Dst, Src)
if Item[0] == '=':
logs.log_errx(112, '"=" assign in edged always %s' % str(Item))
def buildTable(Mod, Path, Env):
for Dst, Src, _, _ in Mod.hard_assigns:
Dsts = support_set(Dst, False)
Srcs = support_set(Src, False)
for S in Srcs:
for D in Dsts:
recordTable(Path + '.' + S, Path + '.' + D)
for Inst in Mod.insts:
Obj = Mod.insts[Inst]
Type = Obj.Type
if Type in Env.Modules:
Son = Env.Modules[Type]
for Pin in Obj.conns:
Nets = support_set(Obj.conns[Pin], False)
Dir, _ = Son.nets[Pin]
if 'output' in Dir:
for Net in Nets:
recordTable(Path + '.' + Inst + '.' + Pin,
Path + '.' + Net)
elif 'input' in Dir:
for Net in Nets:
recordTable(Path + '.' + Net,
Path + '.' + Inst + '.' + Pin)
else:
logs.log_error('strange dir %s of %s in %s' %
(Dir, Pin, Type))
for When, Body, _ in Mod.alwayses:
if combiAlways(When, Mod.Module):
scanBody(Body, [], Path)
for Inst in Mod.insts:
Obj = Mod.insts[Inst]
Type = Obj.Type
if Type in Env.Modules:
Son = Env.Modules[Type]
buildTable(Son, Path + '.' + Inst, Env)
def scanForRegs(Struct):
Regs = []
if (type(Struct) == types.ListType) and (len(Struct) == 1):
return scanForRegs(Struct[0])
if Struct == []: return []
if (type(Struct) in [types.TupleType, types.ListType
]) and (Struct[0] in ['=', '<=']):
Nets = module_class.support_set(Struct[1], False)
for Net in Nets:
if Net not in Regs: Regs.append(Net)
return Regs
if (type(Struct) == types.ListType) and (Struct[0] == 'list'):
for Item in Struct:
More = scanForRegs(Item)
for Net in More:
if Net not in Regs: Regs.append(Net)
return Regs
if (type(Struct) == types.ListType):
if (Struct[0] == 'comment'):
return []
if (Struct[0] == 'if'):
return scanForRegs(Struct[2])
if (Struct[0] == 'ifelse'):
More = scanForRegs(Struct[2]) + scanForRegs(Struct[3])
for Net in More:
if Net not in Regs: Regs.append(Net)
return Regs
if (Struct[0] == 'case'):
LL = Struct[2]
for Case in LL:
PP = Case[1]
More = scanForRegs(PP)
for Net in More:
if Net not in Regs: Regs.append(Net)
return Regs
if (Struct[0] == 'for'):
R1 = Struct[1][1]
More = scanForRegs(Struct[4])
return [R1] + More
logs.log_error('scanForRegs encountered(0) "%s"' % str(Struct))
if type(Struct) in [types.StringType, types.IntType]: return []
logs.log_error('scanForRegs encountered(1) "%s"' % str(Struct))
return Regs
def buildConns(Mod):
for Net in Mod.nets:
Dir, _ = Mod.nets[Net]
if 'input' in Dir:
connect(Net, 'input', Mod.Module, Mod.Module)
if 'output' in Dir:
connect(Net, 'output', Mod.Module, Mod.Module)
if 'inout' in Dir:
connect(Net, 'inout', Mod.Module, Mod.Module)
for Inst in Mod.insts:
Obj = Mod.insts[Inst]
Type = Obj.Type
for Pin in Obj.conns:
Con = Obj.conns[Pin]
Sup = support_set(Con)
for Net in Sup:
connect(Net, Pin, Type, Inst)
def travelAlw(Alw,Cond,Params):
if type(Alw) is list:
if Alw[0]=='list':
for AA in Alw[1:]:
travelAlw(AA,Cond,Params)
return
if Alw[0]=='ifelse':
More = support_set(Alw[1],False)
travelAlw(Alw[2],Cond+More,Params)
travelAlw(Alw[3],Cond+More,Params)
return
if Alw[0]=='if':
More = support_set(Alw[1],False)
travelAlw(Alw[2],Cond+More,Params)
return
if Alw[0]=='wait': return
if Alw[0]=='#': return
if Alw[0]=='case':
More = support_set(Alw[1],False)
for Case in Alw[2]:
More2 = support_set(Case[0],False)
travelAlw(Case[1],Cond+More+More2,Params)
return
if Alw[0]=='<=':
Dst = support_set(Alw[1],False)
Src = support_set(Alw[2],False)
adds(Dst,Src,Params)
for D in Dst:
if D not in TERMS: TERMS.append(D)
return
if Alw[0]=='=':
Dst = support_set(Alw[1],False)
Src = support_set(Alw[2],False)
adds(Dst,Src,Params)
return
print('ERROR alw',Alw)
def scanFunctions(wrds, Env, Mod):
Res = []
for Word in wrds:
if Word.startswith('ahbconn('):
Job = Word[8:-1]
if ',' in Job:
wx = Job.split(',')
SL = wx[0]
PI = wx[1]
else:
SL = Job
PI = ''
Str = AHBX.replace('YY', PI)
Str = Str.replace('XX', SL)
Res.extend(Str.split())
elif Word.startswith('apbconn('):
Job = Word[8:-1]
Str = APBX.replace('XX', Job)
Res.extend(Str.split())
elif Word.startswith('conns('):
Son = Word[6:-1]
Env.try_and_load_module(Son, Env)
if Son in Env.Modules:
Sonobj = Env.Modules[Son]
for Net in Sonobj.nets:
Dir, Wid = Sonobj.nets[Net]
if is_external_dir(Dir):
if (type(Wid) is tuple) and (len(Wid) == 2):
Sup = module_class.support_set(Wid)
for Param in Sup:
if Param in Sonobj.parameters:
Mod.parameters[Param] = Sonobj.parameters[
Param]
elif Param in Sonobj.localparams:
Mod.localparams[
Param] = Sonobj.localparams[Param]
Str = '%s=%s%s' % (Net, Net, wids(Wid))
Res.append(Str)
else:
logs.log_error('module %s could not be loaded' % Son)
else:
Res.append(Word)
return Res
def gatherExpressions(Mod):
Dsts = {}
Srcs = {}
Invs = {}
x2s = []
for In in SOURCES:
Srcs[In] = 1
for Dst, Src, _, _ in Mod.hard_assigns:
if type(Dst) is str:
Dsts[Dst] = Src
if (Src[0] == '!') and (len(Src) == 2) and (type(Src[1]) is str):
Invs[Dst] = Src[1]
Sup = module_class.support_set(Src)
for In in Sup:
if (type(In) is str):
if In not in Srcs:
Srcs[In] = 1
else:
Srcs[In] += 1
for Net in Dsts:
if (Net in Srcs) and (Srcs[Net] == 1) and (Net in Mod.nets):
Dir, Wid = Mod.nets[Net]
if Dir == 'wire':
x2s.append(Net)
Deletes = []
Addeds = []
for Inv in Invs.keys():
Src = Invs[Inv]
if Src in x2s:
logs.log_info('x2s driven inverter %s <= %s = %s' %
(Inv, Src, Dsts[Src]))
Expr = Dsts[Src]
if Expr[0] in ('~', '!'):
Addeds.append((Inv, Expr[1]))
Deletes.append(Inv)
Deletes.append(Src)
Ind = 0
while Ind < len(Mod.hard_assigns):
Dst, Src, _, _ = Mod.hard_assigns[Ind]
if Dst in Deletes:
Mod.hard_assigns.pop(Ind)
else:
Ind += 1
for (Dst, Src) in Addeds:
Mod.hard_assigns.append((Dst, Src, '', ''))
Uses = {}
for Inv in Invs.keys():
if Inv in x2s:
Uses[Inv] = Invs[Inv]
Ind = 0
while Ind < len(Mod.hard_assigns):
(Dst, Src, _, _) = Mod.hard_assigns[Ind]
Src1, Done = replaces(Src, Uses)
if Done:
Mod.hard_assigns[Ind] = (Dst, Src1, '', '')
logs.log_info('fixed hard_assign %s %s <- %s' % (Dst, Src1, Src))
Ind += 1
elif (type(Dst) is str) and (Dst in Uses) and (Dst not in SOURCES):
Mod.hard_assigns.pop(Ind)
if Dst in Mod.nets: Mod.nets.pop(Dst)
else:
Ind += 1
def excecuteLine(Mod, wrds, Env):
wrds = scanFunctions(wrds, Env, Mod)
if (wrds[0] == 'source'):
Fname = wrds[1]
os.system(Fname)
return
if (wrds[0] == 'new'):
newModule = wrds[1]
Env.Current = module_class.module_class(newModule)
Env.Modules[newModule] = Env.Current
return
if (wrds[0] == 'load'):
Fname = wrds[1]
Env.read_verilog_file(Fname, Env.rundir, Env)
return
if (wrds[0] == 'assign'):
Mod.add_hard_assign(wrds[1], wrds[2])
if (wrds[0] == 'add_inout'):
add_wires(Mod, 'inout', wrds[1:])
return
if (wrds[0] == 'add_input'):
add_wires(Mod, 'input', wrds[1:])
return
if (wrds[0] == 'add_output'):
add_wires(Mod, 'output', wrds[1:])
return
if (wrds[0] == 'copy_params'):
From = wrds[1]
Other = Env.Modules[From]
for Param in Other.parameters:
Mod.parameters[Param] = Other.parameters[Param]
for Param in Other.localparams:
Mod.localparams[Param] = Other.localparams[Param]
return
if (wrds[0] == 'copy_inst'):
From = wrds[1]
TypeInst = wrds[2]
if From not in Env.Modules:
Env.try_and_load_module(From, Env)
if From not in Env.Modules:
logs.log_error('failed to load "%s" module' % (From))
return
Other = Env.Modules[From]
for Inst in Other.insts:
found = False
if (Inst == TypeInst):
Type = Other.insts[Inst].Type
Mod.add_inst(Other.insts[Inst].Type, Inst)
found = True
elif (Other.insts[Inst].Type == TypeInst):
Mod.add_inst(TypeInst, Inst)
found = True
if found:
Oobj = Other.insts[Inst]
for Pin in Oobj.conns:
Sig = Oobj.conns[Pin]
if (type(Sig) is str) and (Sig in Other.nets):
_, WW = Other.nets[Sig]
if (type(WW) is tuple) and (len(WW) == 2):
Sig = '%s%s' % (Sig, module_class.pr_wid(WW))
Sup = module_class.support_set(WW[0])
for Param in Sup:
if Param in Other.parameters:
Mod.parameters[Param] = Other.parameters[
Param]
elif Param in Other.localparams:
Mod.localparams[Param] = Other.localparams[
Param]
Mod.add_conn(Inst, Pin, module_class.pr_expr(Sig))
for Param in Oobj.params:
Mod.insts[Inst].params[Param] = Oobj.params[Param]
return
if (wrds[0] == 'unconn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
Obj = Mod.insts[Inst]
for Pin in wrds[2:]:
if Pin in Obj.conns:
Obj.conns[Pin] = False
Env.donesx += 1
else:
Obj.conns[Pin] = False
return
if (wrds[0] == 'del_conn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
Obj = Mod.insts[Inst]
for Pin in wrds[2:]:
if Pin in Obj.conns:
Obj.conns.pop(Pin)
else:
logs.log_error('del_conn isnt=%s pin=%s failed' % (Inst, Pin))
return
if (wrds[0] == 'add_conn'):
Inst = wrds[1]
if Inst not in Mod.insts:
logs.log_error('instance %s is not in module' % Inst)
return
add_conns(Mod, Inst, wrds[2:], Env)
return
if (wrds[0] == 'del_inst'):
for Inst in wrds[1:]:
if Inst in Mod.insts:
Mod.insts.pop(Inst)
Env.donesx += 1
else:
logs.log_error('del instance %s is not in module' % Inst)
return
if (wrds[0] == 'del_wire'):
for Net in wrds[1:]:
if Net in Mod.nets:
Mod.nets.pop(Net)
Env.donesx += 1
else:
logs.log_error('net %s is not in module' % Net)
return
if (wrds[0] == 'add_inst'):
Type = wrds[1]
Inst = wrds[2]
Mod.add_inst(Type, Inst)
add_conns(Mod, Inst, wrds[3:], Env)
return
if (wrds[0] == 'add_param'):
Inst = wrds[1]
for PrmVal in wrds[2:]:
Prm, Val = PrmVal.split('=')
Mod.add_inst_param(Inst, Prm, Val)
return
if (wrds[0] == 'add_wire'):
Dir = wrds[1]
Wid = eval(wrds[2])
for Net in wrds[3:]:
Mod.add_sig(Net, Dir, Wid)
return
if (wrds[0] == 'rename_inst'):
Old = wrds[1]
New = wrds[2]
if Old not in Mod.insts:
logs.log_error('inst %s is not in module' % (Old))
return
Obj = Mod.insts.pop(Old)
Obj.Name = New
Mod.insts[New] = Obj
return
if (wrds[0] == 'retype_inst'):
Old = wrds[1]
Type = wrds[2]
if len(wrds) >= 4:
New = wrds[3]
else:
New = Old
if Old not in Mod.insts:
logs.log_error('inst %s / %s is not in module' % (Type, Old))
return
Obj = Mod.insts[Old]
Obj.Type = Type
Obj.Name = New
if Old != New:
Mod.insts.pop(Old)
Mod.insts[New] = Obj
Env.donesx += 1
return
if (wrds[0] == 'report_connectivity'):
report_connectivity(Mod, Env)
pairsTable(Mod)
singlesTable(Mod)
return
if (wrds[0] == 'remove_unused_wires'):
removeUnused(Mod)
return
if (wrds[0] == 'elaborateSimpleAssigns'):
elaborateSimpleAssigns(Mod)
return
if (wrds[0] == 'assign'):
treatAssigns(Env, Mod, wrds[1], wrds[2])
return
if (wrds[0] == 'save'):
Fname = wrds[1]
execute_line('dump_verilog %s' % Fname, Env)
return
if wrds[0].startswith('remove_gen'):
Mod.generates = []
return
if wrds[0] == 'new_hierarchy':
Mod.prepareNetTable()
Mod.mergeNetTableBusses()
Name = wrds[1]
New = module_class.module_class(Name)
Env.Modules[Name] = New
Insts = wrds[2:]
for Inst in wrds[2:]:
if Inst in Mod.insts:
Obj = Mod.insts[Inst]
New.insts[Inst] = Obj
Mod.insts.pop(Inst)
Nets = list(Mod.nets.keys())
Mod.insts[Name] = module_class.instance_class(Name, Name)
for Net in Nets:
if Net in Mod.netTable:
List = Mod.netTable[Net]
In, Out = False, False
for (Pin, Inst, Type) in List:
if Inst in Insts: In = True
if Inst in Mod.insts: Out = True
if In and not Out:
New.nets[Net] = Mod.nets[Net]
Mod.nets.pop(Net)
elif In and Out:
Dir, Wid = Mod.nets[Net]
New.nets[Net] = 'inout', Wid
Mod.insts[Name].conns[Net] = Net
Fout = open('%s.v' % Name, 'w')
New.dump_verilog(Fout)
Fout.close()
logs.log_error('bad command line %s' % ' '.join(wrds))
