def add_placeholder_inputs(m: MixedSignalModel,
f: PlaceholderFunction,
prefix: str = ''):
# determine the real-number type
real_type = get_dragonphy_real_type()
# data inputs (one for each order of the piecewise-polynomial spline)
wdata = []
for k in range(f.order + 1):
# determine the formatting for the data input
kwargs = {'name': f'{prefix}wdata{k}'}
if real_type in {RealType.FixedPoint, RealType.FloatReal}:
kwargs['signed'] = True
kwargs['width'] = f.coeff_widths[k]
elif real_type == RealType.HardFloat:
kwargs['width'] = DEF_HARD_FLOAT_WIDTH
else:
raise Exception('Unsupported RealType.')
# add the data
wdata += [m.add_digital_input(**kwargs)]
# address input
waddr = m.add_digital_input(f'{prefix}waddr', width=f.addr_bits)
# write enable input
we = m.add_digital_input(f'{prefix}we')
return wdata, waddr, we
def main():
tau = 1e-6
dt = 0.1e-6
model = MixedSignalModel('model', dt=dt)
model.add_analog_input('v_in')
model.add_analog_output('v_out', init=1.23)
model.add_eqn_sys([Deriv(model.v_out) == (model.v_in - model.v_out)/tau])
model.compile_and_print(VerilogGenerator())
def main():
dt = 0.1e-6
m = MixedSignalModel('model', dt=dt)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_eqn_sys([m.v_out == 0.123 * m.v_in])
m.compile_and_print(VerilogGenerator())
def main():
dt = 0.1e-6
num = (1e12,)
den = (1, 8e5, 1e12,)
model = MixedSignalModel('model', dt=dt)
model.add_analog_input('v_in')
model.add_analog_output('v_out')
model.set_tf(input_=model.v_in, output=model.v_out, tf=(num, den))
model.compile_and_print(VerilogGenerator())
def main():
model = MixedSignalModel('model')
model.add_analog_input('a')
model.add_analog_input('b')
model.bind_name('c', model.a + model.b)
model.compile_and_print(VerilogGenerator())
def gen_model(cap=0.16e-6, ind=0.16e-6, res=0.1, dt=0.01e-6,
real_type=RealType.FixedPoint):
# declare model
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('clk')
m.add_digital_input('rst')
# declare system of equations
m.add_analog_state('i_ind', 10) # TODO: can this be tightened down a bit?
v_l = AnalogSignal('v_l')
v_r = AnalogSignal('v_r')
eqns = [
Deriv(m.i_ind) == v_l / ind,
Deriv(m.v_out) == m.i_ind / cap,
v_r == m.i_ind * res,
m.v_in == m.v_out + v_l + v_r
]
m.add_eqn_sys(eqns, clk=m.clk, rst=m.rst)
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
return model_file
def gen_model(rp1, rn1, rp2, rn2, real_type, dt=0.1e-6):
# declare model
m = MixedSignalModel('model', dt=dt, real_type=real_type)
# declare I/O
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('sw1')
m.add_digital_input('sw2')
# declare switch circuit
c = m.make_circuit()
gnd = c.make_ground()
c.voltage('net_v_in', gnd, m.v_in)
c.switch('net_v_in', 'net_v_x', m.sw1, r_on=rp1, r_off=rn1)
c.switch('net_v_x', gnd, m.sw2, r_on=rp2, r_off=rn2)
c.add_eqns(AnalogSignal('net_v_x') == m.v_out)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(real_type):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_analog_output('g')
# bind expression to internal signal
m.add_digital_param('param_a')
m.add_digital_param('param_b')
m.add_digital_param('param_c', width=2, signed=True)
m.add_digital_param('param_d', width=2, signed=True)
m.add_real_param('param_e')
m.add_real_param('param_f')
# create state signals
m.add_digital_state('sig1', init=m.param_a)
m.add_digital_state('sig2', init=m.param_c, width=2, signed=True)
m.add_analog_state('sig3', init=m.param_e, range_=25)
# create main logic
m.set_next_cycle(m.sig1, m.param_b, clk=m.clk, rst=m.rst)
m.set_next_cycle(m.sig2, m.param_d, clk=m.clk, rst=m.rst)
m.set_next_cycle(m.sig3, m.param_f, clk=m.clk, rst=m.rst)
# sum signals to output
m.set_this_cycle(m.g, m.sig1 + m.sig2 + m.sig3)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(tau, real_type):
# create mixed-signal model
m = MixedSignalModel('model', build_dir=BUILD_DIR, real_type=real_type)
# define I/O
x = m.add_analog_input('x')
dt = m.add_analog_input('dt')
y = m.add_analog_output('y')
clk = m.add_digital_input('clk')
rst = m.add_digital_input('rst')
# create function
func = m.make_function(lambda t: np.exp(-t / tau),
domain=[0, 1e-6],
order=1)
# apply function
f = m.set_from_sync_func('f', func, dt, clk=clk, rst=rst)
# update output
x_prev = m.cycle_delay(x, 1, clk=clk, rst=rst)
y_prev = m.cycle_delay(y, 1, clk=clk, rst=rst)
m.set_this_cycle(y, f * y_prev + (1 - f) * x_prev)
# write the model
return m.compile_to_file(VerilogGenerator())
def gen_model(r_off=2.6e3, current_range=100, real_type=RealType.FixedPoint):
# declare model
m = MixedSignalModel('model', dt=1e-9, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('sw1')
m.add_digital_input('sw2')
m.add_digital_input('clk')
m.add_digital_input('rst')
# create test circuit
c = m.make_circuit(clk=m.clk, rst=m.rst)
gnd = c.make_ground()
c.voltage('net_v_in', gnd, m.v_in)
c.switch('net_v_in', 'net_v_x', m.sw1, r_off=r_off)
c.switch('net_v_x', gnd, m.sw2, r_off=r_off)
c.inductor('net_v_in', 'net_v_x', 1.0, current_range=current_range)
c.add_eqns(AnalogSignal('net_v_x') == m.v_out)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def main():
ctrl = ExampleControl()
# create the model
model = MixedSignalModel('bitwise',
DigitalInput('a'),
DigitalInput('b'),
DigitalOutput('a_and_b'),
DigitalOutput('a_or_b'),
DigitalOutput('a_xor_b'),
DigitalOutput('a_inv'),
DigitalOutput('b_inv'),
dt=ctrl.dt)
model.set_this_cycle(model.a_and_b, model.a & model.b)
model.set_this_cycle(model.a_or_b, model.a | model.b)
model.set_this_cycle(model.a_xor_b, model.a ^ model.b)
model.set_this_cycle(model.a_inv, ~model.a)
model.set_this_cycle(model.b_inv, ~model.b)
# write model
ctrl.write_model(model)
def main(num=(1e12, ), den=(
1,
8e5,
1e12,
)):
print('Running model generator...')
# parse command line arguments
parser = ArgumentParser()
parser.add_argument('-o', '--output', type=str)
parser.add_argument('--dt', type=float)
args = parser.parse_args()
# create the model
model = MixedSignalModel('filter',
AnalogInput('v_in'),
AnalogOutput('v_out'),
dt=args.dt)
model.set_tf(input_=model.v_in, output=model.v_out, tf=(num, den))
# determine the output filename
filename = os.path.join(get_full_path(args.output),
f'{model.module_name}.sv')
print('Model will be written to: ' + filename)
# generate the model
model.compile_to_file(VerilogGenerator(), filename)
def gen_model(order, numel, build_dir):
# settings:
# order=0, numel=512 => rms_error <= 0.0105
# order=1, numel=128 => rms_error <= 0.000318
# order=2, numel= 32 => rms_error <= 0.000232
# create mixed-signal model
m = MixedSignalModel('model', build_dir=build_dir)
m.add_analog_input('in_')
m.add_analog_output('out')
# create function
real_func = m.make_function(myfunc,
domain=[-np.pi, +np.pi],
order=order,
numel=numel)
# apply function
m.set_from_sync_func(m.out, real_func, m.in_)
# write the model
return m.compile_to_file(VerilogGenerator())
def main():
dt = 0.1e-6
res = 1e3
cap = 1e-9
m = MixedSignalModel('model', dt=dt)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
c = m.make_circuit()
gnd = c.make_ground()
c.capacitor('net_v_out', gnd, cap, voltage_range=RangeOf(m.v_out))
c.resistor('net_v_in', 'net_v_out', res)
c.voltage('net_v_in', gnd, m.v_in)
c.add_eqns(AnalogSignal('net_v_out') == m.v_out)
m.compile_and_print(VerilogGenerator())
def gen_model(const=1.23, real_type=RealType.FixedPoint):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_analog_input('a')
m.add_analog_output('b')
m.add_eqn_sys([m.b == const * m.a])
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def main():
print('Running model generator...')
# parse command line arguments
parser = ArgumentParser()
parser.add_argument('-o', '--output', type=str, default='build')
parser.add_argument('--dt', type=float, default=0.1e-6)
parser.add_argument('--tau', type=float, default=1.0e-6)
a = parser.parse_args()
# create the model
m = MixedSignalModel('model', dt=a.dt)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
# apply dynamics
m.set_next_cycle(m.v_out, m.v_out*exp(-a.dt/a.tau) + m.v_in*(1-exp(-a.dt/a.tau)))
# determine the output filename
filename = Path(a.output).resolve() / f'{m.module_name}.sv'
print(f'Model will be written to: {filename}')
# generate the model
m.compile_to_file(VerilogGenerator(), filename)
def main(cap=1e-12, res=600):
ctrl = ExampleControl()
# define ports
m = MixedSignalModel('current_switch', dt=ctrl.dt)
m.add_digital_input('ctrl')
m.add_analog_input('v_in')
m.add_analog_output('v_out')
# define the circuit
c = m.make_circuit()
gnd = c.make_ground()
c.switch('net_v_in', 'net_v_out', m.ctrl, r_on=res, r_off=10e3 * res)
c.capacitor('net_v_out', gnd, cap, voltage_range=RangeOf(m.v_out))
c.voltage('net_v_in', gnd, m.v_in)
c.add_eqns(m.v_out == AnalogSignal('net_v_out'))
# write model
ctrl.write_model(m)
def gen_model(real_type):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_analog_input('a')
m.add_analog_input('b')
# bind expression to internal signal
m.bind_name('c', m.a + m.b)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(width, init, real_type):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_digital_output('out', width=width)
# bind expression to internal signal
lfsr = m.lfsr_signal(width, clk=m.clk, rst=m.rst, init=init)
m.set_this_cycle(m.out, lfsr)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(tau=1e-6, dt=0.1e-6, real_type=RealType.FixedPoint):
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('clk')
m.add_digital_input('rst')
m.set_tf(input_=m.v_in,
output=m.v_out,
tf=((1, ), (tau, 1)),
clk=m.clk,
rst=m.rst)
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
return model_file
def gen_model():
# declare model I/O
m = MixedSignalModel('model')
m.add_digital_input('a', width=63, signed=True)
m.add_digital_input('b', width=63, signed=True)
m.add_digital_output('c', width=64, signed=True)
# assign expression to output
m.bind_name('d', m.a - m.b)
m.set_this_cycle(m.c, m.d)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model():
# declare module
m = MixedSignalModel('model')
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_digital_input('seed', width=32)
m.add_digital_output('out', width=32)
# sum signals to output
m.set_this_cycle(m.out, mt19937(clk=m.clk, rst=m.rst, seed=m.seed))
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(n, vn, vp, dt, real_type):
# declare model I/O
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_digital_input('d_in', width=n, signed=True)
m.add_analog_output('a_out')
# compute expression for DAC output
expr = ((m.d_in + (2**(n - 1))) / ((2**n) - 1)) * (vp - vn) + vn
# assign expression to output
m.set_this_cycle(m.a_out, expr)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def main(cap=0.16e-6, ind=0.16e-6, res=0.1):
print('Running model generator...')
# parse command line arguments
parser = ArgumentParser()
parser.add_argument('-o', '--output', type=str)
parser.add_argument('--dt', type=float)
args = parser.parse_args()
# create the model
model = MixedSignalModel('rlc',
AnalogInput('v_in'),
AnalogOutput('v_out'),
dt=args.dt)
model.add_analog_state('i_ind', 100)
# internal variables
v_l = AnalogSignal('v_l')
v_r = AnalogSignal('v_r')
# define dynamics
eqns = [
Deriv(model.i_ind) == v_l / ind,
Deriv(model.v_out) == model.i_ind / cap, v_r == model.i_ind * res,
model.v_in == model.v_out + v_l + v_r
]
model.add_eqn_sys(eqns)
# define probes
#model.add_probe(model.i_ind)
# determine the output filename
filename = os.path.join(get_full_path(args.output),
f'{model.module_name}.sv')
print('Model will be written to: ' + filename)
# generate the model
model.compile_to_file(VerilogGenerator(), filename)
def gen_model(res=1e3, cap=1e-9, dt=0.1e-6, real_type=RealType.FixedPoint):
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('clk')
m.add_digital_input('rst')
c = m.make_circuit(clk=m.clk, rst=m.rst)
gnd = c.make_ground()
c.capacitor('net_v_out', gnd, cap, voltage_range=RangeOf(m.v_out))
c.resistor('net_v_in', 'net_v_out', res)
c.voltage('net_v_in', gnd, m.v_in)
c.add_eqns(AnalogSignal('net_v_out') == m.v_out)
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
return model_file
def gen_model(n, vn, vp, dt, real_type):
# declare model I/O
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('a_in')
m.add_digital_output('d_out', width=n, signed=True)
# compute expression for ADC output as an unclamped, real number
expr = ((m.a_in - vn) / (vp - vn) * ((2**n) - 1)) - (2**(n - 1))
# clamp to ADC range
clamped = clamp_op(expr, -(2**(n - 1)), (2**(n - 1)) - 1)
# assign expression to output
m.set_this_cycle(m.d_out, to_sint(clamped, width=n))
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def main():
print('Running model generator...')
# parse command line arguments
parser = ArgumentParser()
parser.add_argument('-o', '--output', type=str)
parser.add_argument('--dt', type=float, default=0.1e-6)
args = parser.parse_args()
# create the model
m = MixedSignalModel('inertial',
DigitalInput('in_'),
DigitalOutput('out'),
dt=args.dt)
m.set_this_cycle(m.out, m.inertial_delay(m.in_, tr=42e-6, tf=0e-6))
# determine the output filename
filename = os.path.join(get_full_path(args.output), f'{m.module_name}.sv')
print('Model will be written to: ' + filename)
# generate the model
m.compile_to_file(VerilogGenerator(), filename)
def gen_model(tau_f=1e-9,
tau_s=100e-9,
dt=10e-9,
real_type=RealType.FixedPoint):
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('clk')
m.add_digital_input('rst')
m.bind_name('in_gt_out', m.v_in > m.v_out)
# detector dynamics
eqns = [
Deriv(m.v_out) == eqn_case([0, 1 / tau_f], [m.in_gt_out]) *
(m.v_in - m.v_out) - (m.v_out / tau_s)
]
m.add_eqn_sys(eqns, clk=m.clk, rst=m.rst)
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
return model_file
def main(tau=1e-6):
print('Running model generator...')
# parse command line arguments
parser = ArgumentParser()
parser.add_argument('-o', '--output', type=str)
parser.add_argument('--dt', type=float)
args = parser.parse_args()
# create the model
model = MixedSignalModel('filter', DigitalInput('ctrl'), AnalogInput('v_in'), AnalogOutput('v_out'), dt=args.dt)
# define dynamics
model.add_eqn_sys([
Deriv(model.v_out) == eqn_case([0, 1/tau], [model.ctrl])*model.v_in - model.v_out/tau
])
# determine the output filename
filename = os.path.join(get_full_path(args.output), f'{model.module_name}.sv')
print('Model will be written to: ' + filename)
# generate the model
model.compile_to_file(VerilogGenerator(), filename)
def gen_model(real_type):
# create mixed-signal model
model = MixedSignalModel('model', build_dir=BUILD_DIR, real_type=real_type)
model.add_digital_input('in_', width=N_BITS)
model.add_analog_output('out')
model.add_digital_input('clk')
model.add_digital_input('rst')
# create function
domain = [map_f(0), map_f((1 << N_BITS) - 1)]
real_func = model.make_function(
lambda x: inv_cdf(unmap_f(x) / (1 << (N_BITS + 1))),
domain=domain,
order=1,
numel=512)
# apply function
mapped = compress_uint(model.in_)
model.set_from_sync_func(model.out,
real_func,
mapped,
clk=model.clk,
rst=model.rst)
# write the model
return model.compile_to_file(VerilogGenerator())