def test_dmux_multiway(self):
m_one = Multi([one])
m_zero = Multi([zero])
a = dmux_multiway(m_one, m_zero)
b = dmux_multiway(m_one, Multi([zero, one]))
c = dmux_multiway(m_one, Multi([one, one]))
d = dmux_multiway(m_one, Multi([zero, one, one]))
self.assertEquals([str(bit) for bit in a], [str(Multi([one])), str(Multi([zero]))])
self.assertEquals(
[str(bit) for bit in b], [str(Multi([zero])), str(Multi([one])), str(Multi([zero])), str(Multi([zero]))]
)
self.assertEquals(
[str(bit) for bit in c], [str(Multi([zero])), str(Multi([zero])), str(Multi([zero])), str(Multi([one]))]
)
self.assertEquals(
[str(bit) for bit in d],
[
str(Multi([zero])),
str(Multi([zero])),
str(Multi([zero])),
str(Multi([one])),
str(Multi([zero])),
str(Multi([zero])),
str(Multi([zero])),
str(Multi([zero])),
],
)
def test_dmux_multiway(self):
m_one = Multi([one])
m_zero = Multi([zero])
a = dmux_multiway(m_one, m_zero)
b = dmux_multiway(m_one, Multi([zero, one]))
c = dmux_multiway(m_one, Multi([one, one]))
d = dmux_multiway(m_one, Multi([zero, one, one]))
self.assertEquals(
[str(bit) for bit in a],
[str(Multi([one])), str(Multi([zero]))])
self.assertEquals([str(bit) for bit in b], [
str(Multi([zero])),
str(Multi([one])),
str(Multi([zero])),
str(Multi([zero]))
])
self.assertEquals([str(bit) for bit in c], [
str(Multi([zero])),
str(Multi([zero])),
str(Multi([zero])),
str(Multi([one]))
])
self.assertEquals([str(bit) for bit in d], [
str(Multi([zero])),
str(Multi([zero])),
str(Multi([zero])),
str(Multi([one])),
str(Multi([zero])),
str(Multi([zero])),
str(Multi([zero])),
str(Multi([zero]))
])
def __call__(self, multi, load, address, clock):
inputs = dmux_multiway(Multi([load]), address)
regs = [
Multi(pair[0](multi, pair[1], clock))
for pair in zip(self.reg, inputs)
]
return multimux_multiway(address, *regs)
def test_dmux_multiway(self):
"""Checks that dmux_multiway returns the number of outputs indicated by the selector (1 -> 2, 2 -> 4, 3 -> 8), and sets the
Multi instance indicated by the selector equal to the input, and all other outputs zero"""
m_one = Multi([one])
m_zero = Multi([zero])
a = dmux_multiway(m_one, m_zero)
b = dmux_multiway(m_one, Multi([zero, one]))
c = dmux_multiway(m_one, Multi([one, one]))
d = dmux_multiway(m_one, Multi([zero, one, one]))
e = dmux_multiway(m_zero, Multi([one, one]))
self.assertEquals([str(bit) for bit in a], [str(Multi([one])), str(Multi([zero]))])
self.assertEquals([str(bit) for bit in b], [str(Multi([zero])), str(Multi([one])), str(Multi([zero])), str(Multi([zero]))])
self.assertEquals([str(bit) for bit in c], [str(Multi([zero])), str(Multi([zero])), str(Multi([zero])), str(Multi([one]))])
self.assertEquals([str(bit) for bit in d], [str(Multi([zero])), str(Multi([zero])), str(Multi([zero])), str(Multi([one])),
str(Multi([zero])), str(Multi([zero])), str(Multi([zero])), str(Multi([zero]))])
self.assertEquals([str(bit) for bit in e], [str(Multi([zero])), str(Multi([zero])), str(Multi([zero])), str(Multi([zero]))])
def __call__(self, multi, load, address, clock):
input_address = Multi(address[-1:-4:-1])
reg_address = Multi(address[-4:-(len(address) + 1):-1])
inputs = dmux_multiway(Multi([load]), input_address)
regs = [
Multi(pair[0](multi, pair[1], reg_address, clock))
for pair in zip(self.reg, inputs)
]
return multimux_multiway(input_address, *regs)
def __call__(self, multi, load, address, clock):
inputs = dmux_multiway(Multi([load]), address)
regs = [Multi(pair[0](multi, pair[1], clock)) for pair in zip(self.reg, inputs)]
return multimux_multiway(address, *regs)
def __call__(self, multi, load, address, clock):
input_address = Multi(address[-1:-4:-1])
reg_address = Multi(address[-4:-(len(address) + 1):-1])
inputs = dmux_multiway(Multi([load]), input_address)
regs = [Multi(pair[0](multi, pair[1], reg_address, clock)) for pair in zip(self.reg, inputs)]
return multimux_multiway(input_address, *regs)
