def set_freq(self, freq): freq = (int)(freq * 4294.967295 / 180) freq = int2bin.int2bin(freq, 4) print("origin freq : " + freq) y = self.rev_str(freq) print("reverse freq: " + y) addr = self.rev_str(int2bin.int2bin(0x01, 1)) print("rev addr: " + addr) self.write_oneword(addr, y)
def set_freq(self,channel,freq,update = 1): #num 4byte freq = (int)(freq * 8.589934592) freq = int2bin.int2bin(freq,4) #32bit string if channel == 0: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA0,1),update) #str self.write_reg(self.CFTW0_ADD,4,freq,update) #str elif channel ==1: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA1,1),update) #str self.write_reg(self.CFTW0_ADD,4,freq,update) #str elif channel ==2: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA2,1),update) #str self.write_reg(self.CFTW0_ADD,4,freq,update) #str elif channel ==3: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA3,1),update) #str self.write_reg(self.CFTW0_ADD,4,freq,update) #str
def set_phase(self,channel,phase,update=0): #num 2byte if channel == 0: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA0,1),update) #str & not fresh self.write_reg(self.CPOW0_ADD,2,int2bin.int2bin(phase,2),update) #str ,3 bytes !!! elif channel ==1: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA1,1),update) #str self.write_reg(self.CPOW0_ADD,2,int2bin.int2bin(phase,2),update) #str elif channel ==2: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA2,1),update) #str self.write_reg(self.CPOW0_ADD,2,int2bin.int2bin(phase,2),update) #str elif channel ==3: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA3,1),update) #str self.write_reg(self.CPOW0_ADD,2,int2bin.int2bin(phase,2),update) #str
def set_amp(self,channel,amp,update=1): #num 2byte amp = amp | 0x1000 if channel == 0: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA0,1),update) #str self.write_reg(self.ACR_ADD,3,int2bin.int2bin(amp,3),update) #str ,3 bytes !!! elif channel ==1: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA1,1),update) #str self.write_reg(self.ACR_ADD,3,int2bin.int2bin(amp,3),update) #str elif channel ==2: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA2,1),update) #str self.write_reg(self.ACR_ADD,3,int2bin.int2bin(amp,3),update) #str elif channel ==3: self.write_reg(self.CSR_ADD,1,int2bin.int2bin(self.CSR_DATA3,1),update) #str self.write_reg(self.ACR_ADD,3,int2bin.int2bin(amp,3),update) #str
def set_freq1(self, freq): #freq = 90 freq_in = 26 MOD = 13 R = 1 res = freq / freq_in * R * 32 INT = int(res) print(INT) FRAC = int((res - INT) * MOD) print(FRAC) INT = int2bin.int2bin(INT, 2) INT = INT[-16:] FRAC = int2bin.int2bin(FRAC, 2) FRAC = FRAC[-12:] word1 = "0" + INT + FRAC + "000" MOD = int2bin.int2bin(MOD, 2) MOD = MOD[-12:] word2 = "000" + "0" + "1" + "000000000001" + MOD + "001" R = int2bin.int2bin(R, 2) R = R[-10:] word3 = "0000" + "0000" + R + "00" + "1110" + "1100" + "0010" word4 = "00000000" + "00000000" + "00000100" + "10110011" word5 = "00000000" + "1101" + "11010000" + "0000" + "0011" + "1100" word6 = "00000000" + "1101" + "1000" + "000000000000" + "0101" self.write_oneword(word1) self.write_oneword(word2) self.write_oneword(word3) self.write_oneword(word4) self.write_oneword(word5) self.write_oneword(word6)
def reset(self): self.dds_cs.on() self.dds_clk.off() self.dds_up.off() self.dds_data.off() #reset self.dds_rst.off() time.sleep_us(1) self.dds_rst.on() time.sleep_us(30) self.dds_rst.off() #功能寄存器 init_data = 0xd00000 #20倍频 self.write_reg(self.FR1_ADD,3,int2bin.int2bin(init_data,3))
def set_freq2(self, set_list): for ii in range(6): self.write_oneword(int2bin.int2bin(set_list[ii], 4))