def __call__(self, dut, *args, **kwargs): global _tracing, vcdpath if isinstance(dut, _Block): # now we go bottom-up: so clean up and start over # TODO: consider a warning for the overruled block if _simulator._tracing: _simulator._tracing = 0 _simulator._tf.close() os.remove(vcdpath) else: # deprecated if _tracing: return dut(*args, **kwargs) # skip else: # clean start sys.setprofile(None) from myhdl.conversion import _toVerilog if _toVerilog._converting: raise TraceSignalsError("Cannot use traceSignals while converting to Verilog") if not isinstance(dut, _Block): if not callable(dut): raise TraceSignalsError(_error.ArgType, "got %s" % type(dut)) if _simulator._tracing: raise TraceSignalsError(_error.MultipleTraces) _tracing = 1 try: if self.name is None: name = dut.__name__ if isinstance(dut, _Block): name = dut.func.__name__ else: name = str(self.name) if name is None: raise TraceSignalsError(_error.TopLevelName) if self.directory is None: directory = '' else: directory = self.directory if isinstance(dut, _Block): h = _getHierarchy(name, dut) else: warnings.warn( "\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) h = _HierExtr(name, dut, *args, **kwargs) if self.filename is None: filename = name else: filename = str(self.filename) vcdpath = os.path.join(directory, filename + ".vcd") if path.exists(vcdpath): backup = vcdpath + '.' + str(path.getmtime(vcdpath)) shutil.copyfile(vcdpath, backup) os.remove(vcdpath) vcdfile = open(vcdpath, 'w') _simulator._tracing = 1 _simulator._tf = vcdfile _writeVcdHeader(vcdfile, self.timescale) _writeVcdSigs(vcdfile, h.hierarchy, self.tracelists) finally: _tracing = 0 return h.top
def __call__(self, dut, *args, **kwargs): global _tracing, vcdpath if isinstance(dut, _Block): # now we go bottom-up: so clean up and start over # TODO: consider a warning for the overruled block if _simulator._tracing: _simulator._tracing = 0 _simulator._tf.close() os.remove(vcdpath) else: # deprecated if _tracing: return dut(*args, **kwargs) # skip else: # clean start sys.setprofile(None) from myhdl.conversion import _toVerilog if _toVerilog._converting: raise TraceSignalsError( "Cannot use traceSignals while converting to Verilog") if not isinstance(dut, _Block): if not callable(dut): raise TraceSignalsError(_error.ArgType, "got %s" % type(dut)) if _simulator._tracing: raise TraceSignalsError(_error.MultipleTraces) _tracing = 1 try: if self.name is None: name = dut.__name__ if isinstance(dut, _Block): name = dut.func.__name__ else: name = str(self.name) if name is None: raise TraceSignalsError(_error.TopLevelName) if self.directory is None: directory = '' else: directory = self.directory if isinstance(dut, _Block): h = _getHierarchy(name, dut) else: warnings.warn( "\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) h = _HierExtr(name, dut, *args, **kwargs) if self.filename is None: filename = name else: filename = str(self.filename) vcdpath = os.path.join(directory, filename + ".vcd") if path.exists(vcdpath): if self.tracebackup: backup = vcdpath[:-4] + '.' + str( path.getmtime(vcdpath)) + '.vcd' shutil.copyfile(vcdpath, backup) os.remove(vcdpath) vcdfile = open(vcdpath, 'w') _simulator._tracing = 1 _simulator._tf = vcdfile _writeVcdHeader(vcdfile, self.timescale) _writeVcdSigs(vcdfile, h.hierarchy, self.tracelists) finally: _tracing = 0 return h.top
def __call__(self, func, *args, **kwargs): global _converting if _converting: return func(*args, **kwargs) # skip else: # clean start sys.setprofile(None) from myhdl import _traceSignals if _traceSignals._tracing: raise ToVerilogError("Cannot use toVerilog while tracing signals") if not isinstance(func, _Block): if not callable(func): raise ToVerilogError(_error.FirstArgType, "got %s" % type(func)) _converting = 1 if self.name is None: name = func.__name__ if isinstance(func, _Block): name = func.func.__name__ else: name = str(self.name) if isinstance(func, _Block): try: h = _getHierarchy(name, func) finally: _converting = 0 else: warnings.warn( "\n toVerilog(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) try: h = _HierExtr(name, func, *args, **kwargs) finally: _converting = 0 if self.directory is None: directory = '' else: directory = self.directory vfilename = name + ".v" vpath = os.path.join(directory, vfilename) vfile = open(vpath, 'w') ### initialize properly ### _genUniqueSuffix.reset() arglist = _flatten(h.top) # print h.top _checkArgs(arglist) genlist = _analyzeGens(arglist, h.absnames) siglist, memlist = _analyzeSigs(h.hierarchy) _annotateTypes(genlist) # infer interface if isinstance(func, _Block): # infer interface after signals have been analyzed func._inferInterface() intf = func else: intf = _analyzeTopFunc(func, *args, **kwargs) intf.name = name doc = _makeDoc(inspect.getdoc(func)) self._convert_filter(h, intf, siglist, memlist, genlist) _writeFileHeader(vfile, vpath, self.timescale) _writeModuleHeader(vfile, intf, doc) _writeSigDecls(vfile, intf, siglist, memlist) _convertGens(genlist, vfile) _writeModuleFooter(vfile) vfile.close() # don't write testbench if module has no ports if len(intf.argnames) > 0 and not toVerilog.no_testbench: tbpath = os.path.join(directory, "tb_" + vfilename) tbfile = open(tbpath, 'w') _writeTestBench(tbfile, intf, self.trace) tbfile.close() # build portmap for cosimulation portmap = {} for n, s in intf.argdict.items(): if hasattr(s, 'driver'): portmap[n] = s.driver() else: portmap[n] = s self.portmap = portmap ### clean-up properly ### self._cleanup(siglist) return h.top