Пример #1
0
 def beh_clock():
     clock.next = True
     while True:
         yield delay(d1)
         clock.next = False
         yield delay(d2)
         clock.next = True
Пример #2
0
    def WriteAddress(self, addr, data):
        wbuf = [0xDE, 0xCA, 0x01, 0x00, 0x00, 0x01, 0xFB, 0xAD, 0x00]
        rbuf = [0 for ii in range(9)]

        wbuf[3] = (addr >> 8) & 0xFF
        wbuf[4] = addr & 0xFF
        wbuf[5] = 1
        wbuf[8] = data

        self.Write(wbuf, self.EP2)
        while not self.IsEmpty(self.EP2):
            yield delay(2 * self.IFCLK_TICK)
        while not self.IsData(self.EP6, 9):
            yield delay(2 * self.IFCLK_TICK)

        for i in range(9):
            rbuf[i] = self.Read(self.EP6)

        # The last byte is the previous value of the register, it will not match
        for i in range(8):
            if wbuf[i] != rbuf[i]:
                print("wbuf ", wbuf)
                print("rbuf ", rbuf)
            assert wbuf[i] == rbuf[i], "Write Address Failed wbuf[%d](%02x) != rbuf[%d](%02x)" % (
                i,
                wbuf[i],
                i,
                rbuf[i],
            )
Пример #3
0
    def tbstim():
        print("start simulation")
        fbus.write.next = False
        fbus.write_data.next = 0
        fbus.read.next = False
        fbus.clear.next = False

        print("reset")
        reset.next = reset.active
        yield delay(10)
        reset.next = not reset.active
        yield delay(10)

        print("some clock cycles")
        for ii in range(10):
            yield clock_write.posedge

        print("some writes")
        for ii in range(fifosize):
            fbus.write.next = True
            fbus.write_data.next = ii
            yield clock_write.posedge
        fbus.write.next = False
        yield clock_write.posedge

        for ii in range(fifosize):
            fbus.read.next = True
            yield clock_read.posedge
            print("%d %d %d %d" % (
                fbus.write, fbus.write_data, fbus.read, fbus.read_data,))
        fbus.read.next = False

        print("end simulation")
        raise StopSimulation
Пример #4
0
def decim_tb():
    clk, clk_high, rst= [Signal(bool(0)) for i in range(3)]
    x, y = [Signal(intbv(8)) for i in range(2)]
    R = Signal(intbv(4))
    
    TEST_LENGTH = 25 
    HALF_PERIOD = 10
    
    dut = decimate(clk_high, rst, x, y, R)
    
    @always(delay(HALF_PERIOD*R))
    def clockGen():
        clk.next = not clk
        
    @always(delay(HALF_PERIOD))
    def clockGen_high():
        clk_high.next = not clk_high
        
    @instance
    def stimulus():
        rst.next = 1
        yield delay(HALF_PERIOD*10)
        rst.next = 0
        for i in range(TEST_LENGTH):
            yield clk_high.negedge
            x.next = int(uniform(255))
        raise StopSimulation
            
    return dut, clockGen, clockGen_high, stimulus
Пример #5
0
    def inst():
        yield delay(300 * nsec)

        while 1:
            yield delay(interval - 1)
            yield bus.CLK_I.posedge

            bus.CYC_I.next = 1
            bus.STB_I.next = 1
            bus.WE_I.next = 0

            while 1:
                yield bus.CLK_I.posedge
                if bus.ACK_O or bus.ERR_O:
                    break

            if bus.ACK_O:
                print "ACK", hex(bus.ADR_I), hex(bus.DAT_O & ((1<<(len(bus.DAT_O)-1))-1))

            if bus.ERR_O:
                print "ERR", hex(bus.ADR_I)

            bus.CYC_I.next = 0
            bus.STB_I.next = 0

            bus.ADR_I.next = 0
            if bus.ADR_I != n - 1:
                bus.ADR_I.next = bus.ADR_I + 1
Пример #6
0
    def stimulus():

        #write
        for addr, val in zip(addresses, values):
            
            address.next = intbv( addr)[32:]
            data_in.next = intbv( val, min=-(2**31), max=2**31-1)
            
            write_control.next = 1
            clk.next = 0

            print "Write: addr %i = %d" % ( addr, val)
            yield delay(5)
            write_control.next = 0
            clk.next = 1
            yield delay(5)
        
        #read
        for addr in addresses:
            address.next = intbv( addr)[32:]
            read_control.next = 1
            clk.next = 0
            yield delay(5)
            print "Read: addr %i = %d" % (addr, data_out)
            clk.next = 1
            read_control.next = 0
            yield delay(5)
Пример #7
0
 def test(out, c0, c1, d0, d1, d2, d3):
     yield delay(10)
     for i in range(2):
         d0.next = i
         for j in range(2):
             d1.next = j
             for k in range(2):
                 d2.next = k
                 for l in range(2):
                     d3.next = l
             
                     c0.next = 0
                     c1.next = 0
                     yield delay(10)
                     print "here?", c0, c1, d0, d1, d2, d3, out
                     self.assertEqual(d0, out)
                     
                     c1.next = 1
                     yield delay(10)
                     #print c0, c1, d0, d1, d2, d3, out
                     self.assertEqual(d1, out)
                     
                     c0.next = 1
                     c1.next = 0
                     yield delay(10)
                     #print c0, c1, d0, d1, d2, d3, out
                     self.assertEqual(d2, out)
                     
                     c0.next = 1
                     c1.next = 1
                     yield delay(10)
                     #print c0, c1, d0, d1, d2, d3, out
                     self.assertEqual(d3, out)
Пример #8
0
 def stimulus():
     print('out\tin')
     for k in range(16):
         in_.next = k       
         yield delay(10)                 
         print(out, in_, sep='\t')                      
         yield delay(10)              
 def monitor():
     yield self.rx_ready.posedge, delay(500000)
     yield delay(1)
     print(now())
     self.assertEquals(self.rx_msg, 0x0FFFFFFFFFFF)
     self.assertTrue(self.rx_ready)
     self.stop_simulation()
Пример #10
0
 def tbstim():
   yield delay(10)
   print("{0:<8d} ".format(now()))
   yield delay(1000)
   print("{0:<8d} ".format(now()))
   for _ in range(10):
     yield delay(1000)
Пример #11
0
 def driveClk():
     clk.next = 0
     while True:
         yield delay(lowTime)
         clk.next = 1
         yield delay(highTime)
         clk.next = 0
Пример #12
0
 def clock_driver():
     for i in range(NUM_NIBBLES):
         pclk.next = 0
         yield delay(period / 2)
         pclk.next = 1
         yield delay(period / 2)
     pclk.next = 0    # 80
Пример #13
0
        def test():

            self.rx_ready.next = False
            self.tx_ready.next = False
            yield delay(10)
            self.assertTrue(self.nop)
            self.assertFalse(self.rx_next)

            self.rx_ready.next = True
            self.tx_ready.next = True
            yield delay(10)
            self.assertFalse(self.nop)
            self.assertTrue(self.rx_next)

            self.rx_ready.next = True
            self.tx_ready.next = False
            yield delay(10)
            self.assertTrue(self.nop)
            self.assertFalse(self.rx_next)

            self.rx_ready.next = True
            self.tx_ready.next = True
            yield delay(10)
            self.assertFalse(self.nop)
            self.assertTrue(self.rx_next)

            self.rx_ready.next = False
            self.tx_ready.next = True
            yield delay(10)
            self.assertTrue(self.nop)
            self.assertFalse(self.rx_next)

            self.stop_simulation()
Пример #14
0
 def test(out, a):
     yield delay(10)
     self.assertEqual(Signal(None), a)
     self.assertEqual(Signal(None), out)
     a.next = True
     yield delay(10)
     self.assertEqual(Signal(False), out)
Пример #15
0
 def test(out, c0, c1, d0, d1, d2, d3):
     yield delay(10)
     for i in range(2):
         d0.next = bool(i)
         for j in range(2):
             d1.next = bool(j)
             for l in range(2):
                 d3.next = bool(l)
         
                 c0.next = False
                 c1.next = False
                 yield delay(10)
                 print c0, c1, d0, d1, d2, d3, out
                 self.assertEqual(d0, out)
                 
                 c1.next = True
                 yield delay(10)
                 print c0, c1, d0, d1, d2, d3, out
                 self.assertEqual(d1, out)
                 
                 c0.next = True
                 c1.next = False
                 yield delay(10)
                 print c0, c1, d0, d1, d2, d3, out
                 self.assertEqual(d2, out)
                 
                 c0.next = True
                 c1.next = True
                 yield delay(10)
                 print c0, c1, d0, d1, d2, d3, out
                 self.assertEqual(d3, out)
Пример #16
0
 def test(out, a, b):
     yield delay(10)
     for i in range(2):
         a.next = i
         yield delay(10)
         #print a, b, out
         self.assertEqual(Signal(None), out)
Пример #17
0
    def stimulus():
        for i in range(5):
            if random.random() > 0.25:
                clk.next = 1
            if random.random() > 0.75:
                rst.next = 1

            pc_adder_in.next, data1_in.next, data2_in.next, address32_in.next = [intbv(random.randint(-255, 255)) for i in range(4)]

            rs_in.next, rd_in.next, rt_in.next, func_in.next = [intbv(random.randint(0, 15)) for i in range(4)]

            RegDst_in.next, ALUop_in.next, ALUSrc_in.next = [random.randint(0, 1) for i in range(3)]
            Branch_in.next, MemRead_in.next, MemWrite_in.next = [random.randint(0, 1) for i in range(3)]
            RegWrite_in.next, MemtoReg_in.next = [random.randint(0, 1) for i in range(2)]

            yield delay(1)
            print "-" * 79
            print "%i %i %i | %i %i %i | %i | %i  %i  %i  %i  %i  %i  %i  %i " % (data1_in, data2_in, address32_in,
                                                                                  rs_in, rt_in, rd_in, func_in,
                                                                                  RegDst_in, ALUop_in, ALUSrc_in,
                                                                                  Branch_in, MemRead_in, MemWrite_in,
                                                                                  RegWrite_in, MemtoReg_in)
            print "clk: %i  rst: %i " % (clk, rst)

            print "%i %i %i | %i %i %i | %i | %i  %i  %i  %i  %i  %i  %i  %i " % (data1_out, data2_out, address32_out,
                                                                                  rs_out, rt_out, rd_out, func_out, RegDst_out, ALUop_out, ALUSrc_out,
                                                                                  Branch_out, MemRead_out, MemWrite_out,
                                                                                  RegWrite_out, MemtoReg_out)

            clk.next = 0
            rst.next = 0
            yield delay(1)
Пример #18
0
        def tbstim():
            yield delay(1111)
            yield clock.posedge

            # send a bunch of write packets
            print("send packets")
            save_data = []
            yield emesh.write(0xDEEDA5A5, 0xDECAFBAD, 0xC0FFEE)
            save_data.append(0xDECAFBAD)
            for ii in range(10):
                addr = randint(0, 1024)
                data = randint(0, (2**32)-1)
                save_data.append(data)
                yield emesh.write(addr, data, ii)

            # the other device is a simple loopback, should receive
            # the same packets sent.
            while emesh.txwr_fifo.count > 0:
                print("  waiting ... {}".format(emesh))
                yield delay(8000)

            print("get packets looped back, ")
            while len(save_data) > 0:
                yield delay(8000)
                pkt = emesh.get_packet('wr')
                if pkt is not None:
                    assert pkt.data == save_data[0], \
                        "{} ... {:08X} != {:08X}".format(
                        pkt, int(pkt.data), save_data[0])
                    save_data.pop(0)

            for ii in range(27):
                yield clock.posedge

            raise StopSimulation
Пример #19
0
def fifo_write(tx_data,
         reset,
         re,
         rclk,
         Q,
         we,
         wclk,
         data,
         full,
         afull,
         empty,
         aempty,
         width=None,
         depth=None,
         write_active=active_high,
         write_edge=posedge,
         read_active=active_high,
         read_edge=posedge,
         reset_active=active_low,
         reset_edge=posedge,
         threshold=None,
         max_threshold=None,
         duration=T_9600):
    
    print '-- Writing %s --' % hex(tx_data)
    print 'Write: start'
    we.next = True #write_active()
    wclk.next = True
    data.next = intbv(tx_data)
    yield delay(duration)

    print 'Write: stop'
    we.next = False #write_active()
    wclk.next = False
    yield delay(duration)
Пример #20
0
def rs232_rx(rx, data, duration=T_9600, timeout=MAX_TIMEOUT):
    
    """ Simple rs232 receiver procedure.

    rx -- serial input data
    data -- data received
    duration -- receive bit duration
    
    """

    # wait on start bit until timeout
    yield rx.negedge, delay(timeout)
    if rx == 1:
        raise StopSimulation, "RX time out error"

    # sample in the middle of the bit duration
    yield delay(duration // 2)
    print "RX: start bit"

    for i in range(8):
        yield delay(duration)
        print "RX: %s" % rx
        data[i] = rx

    yield delay(duration)
    print "RX: stop bit"
    print "-- Received %s --" % hex(data)
Пример #21
0
    def stimulus():
        for s in script:
            print s
            yield delay(10)
            if (we):
                we.next = False
                wclk.next = False
            elif (re):
                print Q, s
                assert Q == s[1]
                print 'all good in the hood'
                re.next = False
                rclk.next = False

            yield delay(10)

            if s[0] == 'w':
                we.next = True
                wclk.next = True
                data.next = s[1]
            elif s[0] == 'r':
                re.next = True
                rclk.next = True
            elif s[0] == 'x':
                pass
Пример #22
0
 def testlogic():
     reset.next = 0
     yield delay(15)
     reset.next = 1
     yield delay(20)
     print("Converted! %d" % now())
     raise StopSimulation
Пример #23
0
 def reset_filter():
     input.next = 0
     rst_n.next = LOW
     yield delay(1)
     rst_n.next = HIGH
     yield delay(1)
     self.assertEquals(output, 0)
Пример #24
0
        def tbstim():
            try:
                yield delay(100)
                yield reset.pulse(110)
                yield clock.posedge
                
                for k, reg in regdef.items():
                    if reg.access == 'ro':
                        yield regbus.readtrans(reg.addr)
                        rval = regbus.get_read_data()
                        assert rval == reg.default, \
                            "ro: {:02x} != {:02x}".format(rval, reg.default)
                    else:
                        wval = randint(0, (2**reg.width)-1)
                        yield regbus.writetrans(reg.addr, wval)
                        for _ in range(4):
                            yield clock.posedge
                        yield regbus.readtrans(reg.addr)
                        rval = regbus.get_read_data()
                        assert rval == wval, \
                            "rw: {:02x} != {:02x} @ {:04X}".format(
                                rval, wval, reg.addr)
                yield delay(100)
            except AssertionError as err:
                print("@E: %s".format(err))
                traceback.print_exc()
                asserr.next = True
                for _ in range(10):
                    yield clock.posedge
                raise err

            raise StopSimulation
Пример #25
0
        def tbstim():
            yield delay(1000)
            
            # send a write that should enable all five LEDs
            pkt = CommandPacket(False, address=0x20, vals=[0xFF])
            for bb in pkt.rawbytes:
                uartmdl.write(bb)
            waitticks = int((1/115200.) / 1e-9) * 10 * 28
            yield delay(waitticks) 
            timeout = 100
            yield delay(waitticks) 
            # get the response packet
            for ii in range(PACKET_LENGTH):
                rb = uartmdl.read()
                while rb is None and timeout > 0:
                    yield clock.posedge
                    rb = uartmdl.read()
                    timeout -= 1
                if rb is None:
                    raise TimeoutError

            # the last byte should be the byte written
            assert rb == 0xFF

            yield delay(1000)
            raise StopSimulation
Пример #26
0
    def read(self, port, *args):
        p = self.ram.port[port]

        p.blk.next = False
        first = True
        self.result = []

        for addr in args:
            print "Read: start %s" % hex(addr)
            p.addr.next = intbv(addr)
            p.wen.next = True
            p.clk.next = True
            yield delay(self.duration // 2)
            p.clk.next = False
            yield delay(self.duration // 2)

            if not first:
                self.result.append(intbv(int(p.dout)))
            else:
                first = False

        p.clk.next = True
        yield delay(self.duration // 2)
        p.clk.next = False
        yield delay(self.duration // 2)
        self.result.append(intbv(int(p.dout)))

        p.blk.next = True
Пример #27
0
 def test(out, a):
     yield delay(10)
     for i in range(2):
         a.next = i
         yield delay(10)
         #print a, b, out
         self.assertEqual(not a, out)
Пример #28
0
    def stimulus():
        for i in range(5):

            if random.random() > 0.25:
                clk.next = 1
            if random.random() > 0.75:
                rst.next = 1

            branch_adder_in.next, alu_result_in.next, data2_in.next, wr_reg_in.next = [intbv(random.randint(-255, 255)) for i in range(4)]

            Branch_in.next, MemRead_in.next, MemWrite_in.next, zero_in.next = [random.randint(0, 1) for i in range(4)]
            RegWrite_in.next, MemtoReg_in.next = [random.randint(0, 1) for i in range(2)]

            yield delay(1)
            print "-" * 79
            print "%i %i %i %i | %i | %i  %i  %i  %i  %i " % (branch_adder_in, alu_result_in, data2_in, wr_reg_in, zero_in,
                                                              Branch_in, MemRead_in, MemWrite_in,
                                                              RegWrite_in, MemtoReg_in)
            print "clk: %i  rst: %i " % (clk, rst)

            print "%i %i %i %i | %i | %i  %i  %i  %i  %i " % (branch_adder_out, alu_result_out, data2_out, wr_reg_out, zero_out,
                                                              Branch_out, MemRead_out, MemWrite_out,
                                                              RegWrite_out, MemtoReg_out)

            clk.next = 0
            rst.next = 0
            yield delay(1)
Пример #29
0
 def bench():
     clk.next = 0
     yield delay(1)
     reset.next = 1
     yield delay(1)
     reset.next = 0
     select.next = RAMP
     delta_phase.next = DELTA_PHASE
     threshold.next = HALF
     for i in range(1000):
         yield delay(1)
         clk.next = 1
         yield delay(1)
         clk.next = 0
     select.next = TRIANGLE
     for i in range(1000):
         yield delay(1)
         clk.next = 1
         yield delay(1)
         clk.next = 0
     select.next = SQWAVE
     for i in range(1000):
         yield delay(1)
         clk.next = 1
         yield delay(1)
         clk.next = 0
     select.next = NOISE
     for i in range(1000):
         yield delay(1)
         clk.next = 1
         yield delay(1)
         clk.next = 0
Пример #30
0
 def write_delay(self, tx_data):
     print "Write: start"
     self.data.next = intbv(tx_data)
     self.wclk.next = True
     yield delay(self.duration)
     self.wclk.next = False
     yield delay(self.duration)
     print "Write: stop"
Пример #31
0
 def clkGen():
     while 1:
         yield delay(10)
         clk.next ^= 1
Пример #32
0
 def tbclkw():
     clock.next = False
     while True:
         yield delay(5)
         clock.next = not clock
Пример #33
0
def core_testbench(hex_file):
    """
    Connect the Core to the simulation memory, using wishbone interconnects.
    Assert the core for RESET_TIME.

    Finish the test after TIMEOUT units of time, or a write to toHost register.
    If toHost is different of 1, the test failed.
    """
    clk = Signal(True)
    rst = Signal(False)
    imem = WishboneIntercon()
    dmem = WishboneIntercon()

    toHost = Signal(modbv(0)[32:])

    config = cp.ConfigParser()
    config.read('Simulation/core/algol.ini')

    dut_core = Core(clk_i=clk,
                    rst_i=rst,
                    imem=imem,
                    dmem=dmem,
                    toHost=toHost,
                    IC_ENABLE=config.getboolean('ICache', 'Enable'),
                    IC_BLOCK_WIDTH=config.getint('ICache', 'BlockWidth'),
                    IC_SET_WIDTH=config.getint('ICache', 'SetWidth'),
                    IC_NUM_WAYS=config.getint('ICache', 'Ways'),
                    DC_ENABLE=config.getboolean('DCache', 'Enable'),
                    DC_BLOCK_WIDTH=config.getint('DCache', 'BlockWidth'),
                    DC_SET_WIDTH=config.getint('DCache', 'SetWidth'),
                    DC_NUM_WAYS=config.getint('DCache', 'Ways'))

    memory = Memory(clka_i=clk,
                    rsta_i=rst,
                    imem=imem,
                    clkb_i=clk,
                    rstb_i=rst,
                    dmem=dmem,
                    SIZE=int(config.get('Memory', 'Size'), 16),
                    HEX=hex_file,
                    BYTES_X_LINE=config.getint('Memory', 'Bytes_x_line'))

    @always(delay(int(TICK_PERIOD / 2)))
    def gen_clock():
        clk.next = not clk

    @always(toHost)
    def toHost_check():
        """
        Wait for a write to toHost register.
        """
        if toHost != 1:
            raise Error('Test failed. MTOHOST = {0}. Time = {1}'.format(
                toHost, now()))
        print("Time: {0}".format(now()))
        raise StopSimulation

    @instance
    def timeout():
        """
        Wait until timeout.
        """
        rst.next = True
        yield delay(RESET_TIME * TICK_PERIOD)
        rst.next = False
        yield delay(TIMEOUT * TICK_PERIOD)
        raise Error("Test failed: Timeout")

    return dut_core, memory, gen_clock, timeout, toHost_check
Пример #34
0
 def beh_reset():
     reset.next = reset.active
     yield delay(40)
     yield clock.posedge
     reset.next = not reset.active
Пример #35
0
def clock(clk):
    @always(delay(10))
    def clck():
        clk.next = not clk

    return clck
Пример #36
0
 def stimulus():
     while True:
         yield delay(1)
         print "time: %s | Clock: %i | in: %i | out: %i" % (now(), clk, i,
                                                            o)
Пример #37
0
 def drive_reset():
     reset.next = 0 if active_low else 1
     yield delay(10)
     reset.next = 1 if active_low else 0
Пример #38
0
 def testArgIsNormalFunction(self):
     with raises_kind(AlwaysError, _error.ArgType):
         @always(delay(3))
         def h():
             yield None
Пример #39
0
 def testArgHasNoArgs(self):
     with raises_kind(AlwaysError, _error.NrOfArgs):
         @always(delay(3))
         def h(n):
             return n
Пример #40
0
 def tb_clk():
     clock.next = False
     yield delay(10)
     while True:
         clock.next = not clock
         yield delay(10)
Пример #41
0
 def testArgIsFunction(self):
     h = 5
     with raises_kind(AlwaysError, _error.ArgType):
         always(delay(3))(h)
 def drive_clk():
     while True:
         yield delay(low_time)
         clk.next = 1
         yield delay(high_time)
         clk.next = 0
Пример #43
0
        def tbstim():
            yield reset.pulse(33)
            yield delay(100)
            yield clock.posedge

            try:
                # ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                # loop through the registers and check the default
                # values, these are the offset values.
                for addr, sig in rf.roregs:
                    yield regbus.readtrans(addr + ba)
                    assert regbus.get_read_data() == int(sig), \
                        "Invalid read-only value"

                for addr, sig in rf.rwregs:
                    # need to skip the FIFO read / write
                    if addr in (
                            rf.sptx.addr,
                            rf.sprx.addr,
                    ):
                        pass
                    else:
                        yield regbus.readtrans(addr + ba)
                        assert regbus.get_read_data() == int(sig), \
                            "Invalid default value"

                # ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                # enable the system
                print("enable the SPI core")
                yield regbus.writetrans(rf.spst.addr,
                                        0x02)  # register data drives fifo
                yield regbus.writetrans(rf.spcr.addr,
                                        0x9A)  # default plus enable (98 + 02)

                print("write to the transmit register")
                for data in (0x02, 0x00, 0x00, 0x00, 0x55):
                    print("\nwriting to sptx {:02x}".format(data))
                    yield regbus.writetrans(rf.sptx.addr, data)

                print("")
                yield regbus.readtrans(rf.sptc.addr)
                print("TX FIFO count {}".format(regbus.get_read_data()))

                yield regbus.readtrans(rf.sprc.addr)
                print("RX FIFO count {}".format(regbus.get_read_data()))

                yield delay(1000)

                print("wait for return bytes")
                for ii in range(1000):
                    yield regbus.readtrans(rf.sprc.addr)
                    if regbus.get_read_data() == 5:
                        break
                    yield delay(10)

                # verify bytes received and not timeout
                print("RX FIFO count {}".format(regbus.get_read_data()))
                assert regbus.get_read_data() == 5

                print("read the returned bytes")
                for ii in range(5):
                    yield regbus.readtrans(rf.sprx.addr)
                    print("spi readback {0}".format(regbus.get_read_data()))

            except Exception as err:
                print("@W: exception {0}".format(err))
                yield delay(100)
                traceback.print_exc()
                raise err

            yield delay(100)
            raise StopSimulation
Пример #44
0
        def tbstim():
            fb.ADDR.next = 0
            yield delay(3 * fm.IFCLK_TICK)
            fb.RST.next = False
            yield delay(13 * fm.IFCLK_TICK)
            fb.RST.next = True
            yield delay(13 * fm.IFCLK_TICK)

            # FLAGC is gotdata
            # FLAGB is gotroom
            # In the config1 mode FLAGC is gotdata and FLAGB is gotroom.
            # At start FLAGB == True and FLAGC == False.  After a write
            # FLAGC == True.
            # Config1 onl

            assert fb.FLAGB
            assert not fb.FLAGC

            fm.write([0xCE], fm.EP2)
            yield delay(3 * fm.IFCLK_TICK)
            assert fb.FLAGB  # still should have room
            assert fb.FLAGC  # should have data now
            assert fb.FDO == 0xCE
            assert not fm.isempty(fm.EP2)

            # read out the data written, 1 byte
            yield readtrans(fb, 1)
            assert fb.FLAGB  # still should have room
            assert not fb.FLAGC  # no data now
            assert fm.isempty(fm.EP2)
            yield delay(13 * fm.IFCLK_TICK)

            # Write a burst of data and read the burst of data
            data = list(range(33))
            data[0] = 0xFE
            fm.write(data, fm.EP2)
            yield delay(3 * fm.IFCLK_TICK)
            assert fb.FLAGB  # still should have room
            assert fb.FLAGC  # should have data now
            assert fb.FDO == 0xFE
            assert not fm.isempty(fm.EP2)

            yield readtrans(fb, 33)
            assert fb.FLAGB  # still should have room
            assert not fb.FLAGC  # now data now
            assert fm.isempty(fm.EP2)

            # read one more
            yield readtrans(fb, 1)

            # fill the FIFO
            data = [randint(0, 0xFF) for _ in range(512)]
            fm.write(data, fm.EP2)
            yield delay(3 * fm.IFCLK_TICK)
            assert fb.FLAGB  # still should have room
            assert fb.FLAGC  # should have data now
            assert fb.FDO == data[0]
            assert not fm.isempty(fm.EP2)

            yield readtrans(fb, 512)
            assert fb.FLAGB  # still should have room
            assert not fb.FLAGC  # now data now
            assert fm.isempty(fm.EP2)

            # The model should handle flow, control it will take
            # how much ever data? (this emulates how the host USB
            # software stack would work).
            data = [randint(0, 0xFF) for _ in range(517)]
            fm.write(data, fm.EP2)
            yield delay(3 * fm.IFCLK_TICK)
            assert fb.FLAGB  # still should have room
            assert fb.FLAGC  # should have data now
            assert fb.FDO == data[0]
            assert not fm.isempty(fm.EP2)

            yield readtrans(fb, 512)
            assert fb.FLAGB  # still should have room
            assert fb.FLAGC  # now data now

            yield readtrans(fb, 7)
            assert fb.FLAGB  # still should have room
            assert not fb.FLAGC  # now data now
            assert fm.isempty(fm.EP2)

            raise StopSimulation
 def logic():
     while 1:
         yield delay(10)
         clk.next = not clk
Пример #46
0
def DelayFunc(a, b, c, d, r):
    @always(delay(3))
    def logic():
        r.next = a + b + c + d

    return logic
Пример #47
0
 def gclock():
     self.next = False
     while True:
         yield delay(hticks)
         self.next = not self.val
Пример #48
0
 def testArgIsFunction(self):
     h = 5
     try:
         always(delay(3))(h)
     except AlwaysError, e:
         self.assertEqual(e.kind, _error.ArgType)
Пример #49
0
 def drive_system_clock():
     while True:
         yield delay(low_time)
         system_clock.next = 1
         yield delay(high_time)
         system_clock.next = 0
Пример #50
0
    def stimulus():

        # Test Branch Instructions
        branch_instr = ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu']
        for i in range(len(branch_instr)):
            instruction.next = intbv(int(test_instruction[branch_instr[i]],
                                         2))[32:]
            yield delay(10)
            assert (bin(rs1, width=5) == '00010')
            assert (bin(rs2, width=5) == '00001')
            assert (bin(imm12lo, width=6) == '010000')
            assert (bin(imm12hi, width=6) == '000000')
            assert (bin(opcode, width=7) == '1100011')
            assert (bin(arg_select, width=10) == '1100110000')
            if i < 2:
                assert (bin(funct3, width=3) == bin(i, width=3))
            else:
                assert (bin(funct3, width=3) == bin(i + 2, width=3))

        # Test LUI and AUIPC Instructions
        lui_auipc_instr = ['lui', 'auipc']
        for i in range(len(lui_auipc_instr)):
            instruction.next = intbv(
                int(test_instruction[lui_auipc_instr[i]], 2))[32:]
            yield delay(10)
            assert (bin(rd, width=5) == '00001')
            assert (bin(arg_select, width=10) == '0010000100')
            assert (bin(imm20, width=20) == '00000000000000000001')
            if i == 0:
                assert (bin(opcode, width=7) == '0110111')
            else:
                assert (bin(opcode, width=7) == '0010111')

        # Test Jump Instructions
        jump_instr = ['jalr', 'jal']
        for i in range(len(jump_instr)):
            instruction.next = intbv(int(test_instruction[jump_instr[i]],
                                         2))[32:]
            yield delay(10)
            assert (bin(rd, width=5) == '00001')
            if i == 0:
                assert (bin(imm12, width=12) == '000000000001')
                assert (bin(rs1, width=5) == '00001')
                assert (bin(arg_select, width=10) == '1010001000')
                assert (bin(opcode, width=7) == '1100111')
            else:
                assert (bin(imm20, width=20) == '10001100010000000001')
                assert (bin(arg_select, width=10) == '0010000100')
                assert (bin(opcode, width=7) == '1101111')

        # Test Addition and Logical immediate Instructions
        arith_logic_imm_instr = [
            'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori',
            'andi'
        ]
        for i in range(len(arith_logic_imm_instr)):
            instruction.next = intbv(
                int(test_instruction[arith_logic_imm_instr[i]], 2))[32:]
            yield delay(10)
            assert (bin(rd, width=5) == '00001')
            assert (bin(rs1, width=5) == '00001')
            assert (bin(opcode, width=7) == '0010011')
            if i in [1, 5, 6]:
                assert (bin(arg_select, width=10) == '1010000010')
                assert (bin(shamt, width=5) == '00001')
            else:
                assert (bin(imm12, width=12) == '000000000001')
                assert (bin(arg_select, width=10) == '1010001000')

        # Test Addition and Logical Reg to Reg Instructions
        arith_logic_r2r_instr = [
            'add', 'sll', 'slt', 'sltu', 'xor', 'srl', 'or', 'and', 'sub',
            'sra'
        ]
        for i in range(len(arith_logic_r2r_instr)):
            instruction.next = intbv(
                int(test_instruction[arith_logic_r2r_instr[i]], 2))[32:]
            yield delay(10)
            assert (bin(rd, width=5) == '00011')
            assert (bin(rs1, width=5) == '00001')
            assert (bin(rs2, width=5) == '00010')
            assert (bin(opcode, width=7) == '0110011')
            assert (bin(arg_select, width=10) == '1110000000')
            if i == 8:
                assert (bin(funct3, width=3) == bin(0, width=3))
            elif i == 9:
                assert (bin(funct3, width=3) == bin(5, width=3))
            else:
                assert (bin(funct3, width=3) == bin(i, width=3))

        # Test Load Instructions
        load_instr = ['lb', 'lh', 'lw', 'lbu', 'lhu']
        for i in range(len(load_instr)):
            instruction.next = intbv(int(test_instruction[load_instr[i]],
                                         2))[32:]
            yield delay(10)
            assert (bin(rd, width=5) == '00010')
            assert (bin(rs1, width=5) == '00001')
            assert (bin(imm12, width=12) == '000000000001')
            assert (bin(opcode, width=7) == '0000011')
            assert (bin(arg_select, width=10) == '1010001000')
            if i <= 2:
                assert (bin(funct3, width=3) == bin(i, width=3))
            else:
                assert (bin(funct3, width=3) == bin(i + 1, width=3))

        # Test Store Instructions
        store_instr = ['sb', 'sh', 'sw']
        for i in range(len(store_instr)):
            instruction.next = intbv(int(test_instruction[store_instr[i]],
                                         2))[32:]
            yield delay(10)
            assert (bin(rs1, width=5) == '00010')
            assert (bin(rs2, width=5) == '00001')
            assert (bin(imm12, width=12) == '000001000001')
            assert (bin(opcode, width=7) == '0100011')
            assert (bin(arg_select, width=10) == '1100001000')
            assert (bin(funct3, width=3) == bin(i, width=3))

        # Test System Instructions
        sys_instr = [
            'ecall', 'ebreak', 'rdcycle', 'rdcycleh', 'rdtime', 'rdtimeh',
            'rdinstret', 'rdinstreth'
        ]
        for i in range(len(sys_instr)):
            instruction.next = intbv(int(test_instruction[sys_instr[i]],
                                         2))[32:]
            yield delay(10)
            assert (bin(opcode, width=7) == '1110011')
            if i in [0, 1]:
                assert (bin(arg_select, width=10) == '0000001000')
                assert (bin(funct3, width=3) == bin(0, width=3))
                assert (bin(imm12, width=12) == bin(i, width=12))
            else:
                assert (bin(arg_select, width=10) == '0010001000')
                assert (bin(funct3, width=3) == bin(2, width=3))
                assert (bin(rd, width=5) == '00001')
                sys_imms = [
                    '110000000000', '110010000000', '110000000001',
                    '110010000001', '110000000010', '110010000010'
                ]
                assert (bin(imm12, width=12) == sys_imms[i - 2])
Пример #51
0
def clk_driver(iClk, period=10):
    ''' Clock driver '''
    @always(delay(period//2))
    def driver():
        iClk.next = not iClk
    return driver
Пример #52
0
 def tbstim():
     # @todo: add test stimulus
     yield delay(10)
     raise StopSimulation
Пример #53
0
def pulse_reset(reset, clock):
    reset.next = reset.active
    yield delay(40)
    yield clock.posedge
    reset.next = not reset.active
    yield clock.posedge
Пример #54
0
 def test():
     self.MemRead_ex.next = 0
     yield delay(1)
     self.assertEqual(int(self.Stall), 0)
Пример #55
0
 def stimulus():
     print("z a b sel")
     for i in range(12):
         a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2)
         yield delay(10)
         print("%s %s %s %s" % (z, a, b, sel))
def test_dim0(n=10, step_word=0.5, step_context=0.5):
    """Testing bench around zero in dimension 0."""

    embedding_dim = 3
    leaky_val = 0.01
    fix_min = -2**7
    fix_max = -fix_min
    fix_res = 2**-8
    fix_width = 1 + 7 + 8

    # signals
    y = Signal(fixbv(0.0, min=fix_min, max=fix_max, res=fix_res))
    y_dword_vec = Signal(intbv(0)[embedding_dim * fix_width:])
    y_dcontext_vec = Signal(intbv(0)[embedding_dim * fix_width:])
    y_dword_list = [
        Signal(fixbv(0.0, min=fix_min, max=fix_max, res=fix_res))
        for j in range(embedding_dim)
    ]
    y_dcontext_list = [
        Signal(fixbv(0.0, min=fix_min, max=fix_max, res=fix_res))
        for j in range(embedding_dim)
    ]
    for j in range(embedding_dim):
        y_dword_list[j].assign(y_dword_vec((j + 1) * fix_width, j * fix_width))
        y_dcontext_list[j].assign(
            y_dcontext_vec((j + 1) * fix_width, j * fix_width))

    word_emb = [
        Signal(fixbv(0.0, min=fix_min, max=fix_max, res=fix_res))
        for _ in range(embedding_dim)
    ]
    word_embv = ConcatSignal(*reversed(word_emb))
    context_emb = [
        Signal(fixbv(0.0, min=fix_min, max=fix_max, res=fix_res))
        for _ in range(embedding_dim)
    ]
    context_embv = ConcatSignal(*reversed(context_emb))

    clk = Signal(bool(False))

    # modules
    wcprod = WordContextProduct(y, y_dword_vec, y_dcontext_vec, word_embv,
                                context_embv, embedding_dim, leaky_val,
                                fix_min, fix_max, fix_res)

    # test stimulus
    HALF_PERIOD = delay(5)

    @always(HALF_PERIOD)
    def clk_gen():
        clk.next = not clk

    @instance
    def stimulus():
        yield clk.negedge

        for i in range(n):
            # new values
            word_emb[0].next = fixbv(step_word * i - step_word * n // 2,
                                     min=fix_min,
                                     max=fix_max,
                                     res=fix_res)
            context_emb[0].next = fixbv(step_context * i,
                                        min=fix_min,
                                        max=fix_max,
                                        res=fix_res)

            yield clk.negedge
            print "%3s word: %s, context: %s, y: %f, y_dword: %s, y_dcontext: %s" % (
                now(), [float(el.val) for el in word_emb], [
                    float(el.val) for el in context_emb
                ], y, [float(el.val) for el in y_dword_list
                       ], [float(el.val) for el in y_dcontext_list])

        raise StopSimulation()

    return clk_gen, stimulus, wcprod
Пример #57
0
 def stimulus():
     # NOTE: 1e9 equals 1 second
     interval = delay(round(1E9))
     yield interval
     assert 1 == 1
     raise StopSimulation
 def ckgen():
     while 1:
         yield delay(10)
         clk.next = not clk
Пример #59
0
 def reset_gen():
     reset.next = 0
     yield delay(54)
     yield clk.negedge
     reset.next = 1
Пример #60
0
    def runTest(self,
                test,
                grid_dimension_x,
                grid_dimension_y,
                output_core_x_coordinate,
                output_core_y_coordinate,
                num_outputs,
                num_neurons,
                num_axons,
                num_ticks,
                num_weights,
                num_reset_modes,
                potential_width,
                weight_width,
                leak_width,
                threshold_width,
                dx_msb,
                dx_lsb,
                dy_msb,
                dy_lsb,
                input_buffer_depth,
                router_buffer_depth,
                memory_filepath,
                maximum_number_of_packets,
                c_s00_axis_tdata_width,
                correct_filepath,
                delay_ns=10,
                tick_latency=1):

        # Initializing registers
        clk, rst, tick, s00_axis_aclk, s00_axis_aresetn = [
            Signal(bool(0)) for _ in range(5)
        ]
        s00_axis_tdata = Signal(intbv(0)[c_s00_axis_tdata_width:0])
        s00_axis_tstrb = Signal(intbv(0)[(c_s00_axis_tdata_width / 8):0])
        s00_axis_tlast, s00_axis_tvalid = [Signal(bool(0)) for _ in range(2)]

        # Initializing wires
        packet_out = Signal(intbv(0)[num_outputs.bit_length():0])
        packet_out_valid, token_controller_error, scheduler_error, \
            packet_read_error, fifo_write_error, s00_axis_tready = [
                Signal(bool(0)) for _ in range(6)]

        input_ports = InputPorts(clk, rst, tick, s00_axis_aclk,
                                 s00_axis_aresetn, s00_axis_tdata,
                                 s00_axis_tstrb, s00_axis_tlast,
                                 s00_axis_tvalid)

        output_ports = OutputPorts(packet_out, packet_out_valid,
                                   token_controller_error, scheduler_error,
                                   packet_read_error, fifo_write_error,
                                   s00_axis_tready)

        params = Params(grid_dimension_x, grid_dimension_y,
                        output_core_x_coordinate, output_core_y_coordinate,
                        num_outputs, num_neurons, num_axons, num_ticks,
                        num_weights, num_reset_modes, potential_width,
                        weight_width, leak_width, threshold_width, dx_msb,
                        dx_lsb, dy_msb, dy_lsb, input_buffer_depth,
                        router_buffer_depth, memory_filepath,
                        maximum_number_of_packets, c_s00_axis_tdata_width)

        # Registers for the test bench
        counter = Signal(intbv(0)[32:0])
        num_ticks = Signal(intbv(0)[32:0])
        current_correct_line = Signal(intbv(0)[32:0])
        packet_count = Signal(intbv(0)[32:0])

        # Getting all of the correct packets
        correct_file = open(correct_filepath, 'r')

        # Obtaining the cosimulation object
        dut = RANCNetwork(input_ports, output_ports, params)
        """Generating the clock, tick, and checking the output
        against the simulator should be the same for every test
        so just keeping them all in here"""
        @always(delay(delay_ns))
        def clockGen():
            clk.next = not clk
            s00_axis_aclk.next = not s00_axis_aclk

        @always(clk.negedge)
        def tickGen():
            if int(bin(counter.val), 2) == TICK_PERIOD_NS / delay_ns - 1:
                counter.next = 0
                tick.next = 1
                num_ticks.next = num_ticks + 1
            else:
                tick.next = 0
                counter.next = counter + 1

        @always(clk.posedge)
        def checkOutput():
            if (num_ticks > tick_latency and packet_out_valid):
                correct_packet = correct_file.readline().rstrip()
                if DEBUG:
                    print('Tick {}, Packet {}: actual is {},'
                          ' correct is {}'.format(
                              int(bin(num_ticks.val), 2),
                              int(bin(packet_count.val), 2),
                              bin(packet_out.val), correct_packet))
                current_correct_line.next = current_correct_line + 1
                self.assertEqual(int(bin(packet_out.val), 2),
                                 int(correct_packet, 2))

                # Checking if there are more packets to process
                next_correct_packet = peek_line(correct_file)
                if next_correct_packet == '':
                    if DEBUG:
                        print("Test complete. All packets are correct.")
                    raise StopSimulation

                packet_count.next = packet_count + 1

        check = test(input_ports, output_ports, params)

        sim = Simulation(dut, clockGen, tickGen, checkOutput, check)
        sim.run()