def _analyzeGens(top, absnames):
genlist = []
for g in top:
if isinstance(g, _UserCode):
tree = g
elif isinstance(g, (_AlwaysComb, _AlwaysSeq, _Always)):
f = g.func
s = inspect.getsource(f)
s = _dedent(s)
tree = ast.parse(s)
#print ast.dump(tree)
tree.sourcefile = inspect.getsourcefile(f)
tree.lineoffset = inspect.getsourcelines(f)[1]-1
tree.symdict = f.func_globals.copy()
tree.callstack = []
# handle free variables
tree.nonlocaldict = {}
if f.func_code.co_freevars:
for n, c in zip(f.func_code.co_freevars, f.func_closure):
obj = _cell_deref(c)
if isinstance(g, _AlwaysComb):
if not ( isinstance(obj, (int, long, EnumType,_Signal)) or \
_isMem(obj) or _isTupleOfInts(obj)
):
info = "File %s, line %s: " % (tree.sourcefile, tree.lineoffset)
print type(obj)
raise ConversionError(_error.UnsupportedType, n, info)
tree.symdict[n] = obj
# currently, only intbv as automatic nonlocals (until Python 3.0)
if isinstance(obj, intbv):
tree.nonlocaldict[n] = obj
tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
v = _FirstPassVisitor(tree)
v.visit(tree)
if isinstance(g, _AlwaysComb):
v = _AnalyzeAlwaysCombVisitor(tree, g.senslist)
elif isinstance(g, _AlwaysSeq):
v = _AnalyzeAlwaysSeqVisitor(tree, g.senslist, g.reset, g.sigregs, g.varregs)
else:
v = _AnalyzeAlwaysDecoVisitor(tree, g.senslist)
v.visit(tree)
else: # @instance
f = g.gen.gi_frame
s = inspect.getsource(f)
s = _dedent(s)
tree = ast.parse(s)
# print ast.dump(tree)
tree.sourcefile = inspect.getsourcefile(f)
tree.lineoffset = inspect.getsourcelines(f)[1]-1
tree.symdict = f.f_globals.copy()
tree.symdict.update(f.f_locals)
tree.nonlocaldict = {}
tree.callstack = []
tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
v = _FirstPassVisitor(tree)
v.visit(tree)
v = _AnalyzeBlockVisitor(tree)
v.visit(tree)
genlist.append(tree)
return genlist
def raiseError(self, node, kind, msg=""):
lineno = self.getLineNo(node)
info = "in file %s, line %s:\n " % \
(self.tree.sourcefile, self.tree.lineoffset + lineno)
raise ConversionError(kind, msg, info)
def _analyzeSigs(hierarchy, hdl='Verilog'):
curlevel = 0
siglist = []
memlist = []
prefixes = []
open, close = '[', ']'
if hdl == 'VHDL':
open, close = '(', ')'
for inst in hierarchy:
level = inst.level
name = inst.name
sigdict = inst.sigdict
memdict = inst.memdict
delta = curlevel - level
curlevel = level
assert(delta >= -1)
if delta > -1: # same or higher level
prefixes = prefixes[:curlevel-1]
# skip processing and prefixing in context without signals
if not (sigdict or memdict):
prefixes.append("")
continue
prefixes.append(name)
for n, s in sigdict.items():
if s._name is not None:
continue
if isinstance(s, _SliceSignal):
continue
s._name = _makeName(n, prefixes)
if not s._nrbits:
raise ConversionError(_error.UndefinedBitWidth, s._name)
# slice signals
for sl in s._slicesigs:
sl._setName(hdl)
siglist.append(s)
# list of signals
for n, m in memdict.items():
if m.name is not None:
continue
m.name = _makeName(n, prefixes)
memlist.append(m)
# handle the case where a named signal appears in a list also by giving
# priority to the list and marking the signals as unused
for m in memlist:
if not m._used:
continue
for i, s in enumerate(m.mem):
s._name = "%s%s%s%s" % (m.name, open, i, close)
s._used = False
if s._inList:
raise ConversionError(_error.SignalInMultipleLists, s._name)
s._inList = True
if not s._nrbits:
raise ConversionError(_error.UndefinedBitWidth, s._name)
if type(s.val) != type(m.elObj.val):
raise ConversionError(_error.InconsistentType, s._name)
if s._nrbits != m.elObj._nrbits:
raise ConversionError(_error.InconsistentBitWidth, s._name)
return siglist, memlist