def registers(set_val, r1addr, r2addr, setaddr, value, r1 = None, r2 = None, pc = None): nl.push_context("registers") n = nl.get_size(value) regs = [] for i in range(constants.REGISTERS.number): write_enable = nl.fresh() if i == constants.REGISTERS.pc: pc = register_pc(value, write_enable, pc) reg = pc elif i in constants.REGISTERS.inputs: reg = nl.fresh(n) nl.input(reg) else: reg = register(value, write_enable) if i in constants.REGISTERS.outputs: nl.output(reg) regs.append((write_enable, reg)) addr_size = nl.get_size(r1addr) assert(1 << addr_size == constants.REGISTERS.number) r1 = mux_n(addr_size, [r[1] for r in regs], r1addr, r1) r2 = mux_n(addr_size, [r[1] for r in regs], r2addr, r2) demux_n(addr_size, [r[0] for r in regs], set_val, setaddr) nl.pop_context() return r1, r2, pc
def register(data, write_enable, destr = None): n = nl.get_size(data) u = nl.fresh(n) destr = nl.REG(u, destr) write_n = helpers.wire_expand(n, write_enable) nl.MUX(destr, data, write_n, u) return destr
def memory_unit(instr, value, addr, result = None): nl.push_context("memory_unit") is_memory = nl.AND(nl.SELECT(1, instr), nl.SELECT(4, instr)) we = nl.AND(is_memory, nl.SELECT(2, instr)) addr = nl.SLICE(1, 16, addr) if UNUSED_ADDR_ZERO: addr = nl.AND(addr, helpers.wire_expand(16, is_memory)) uu = nl.fresh(16) nl.pop_context() return nl.RAM(16, 64, addr, we, nl.WIRE(addr, uu), value, result)
def register_pc(data, write_enable, destr = None): n = nl.get_size(data) u = nl.fresh(n) destr = nl.REG(u, destr) nl.push_context("incr") incremented, _ = alu.incr(n, destr) nl.pop_context() write_n = helpers.wire_expand(n, write_enable) nl.MUX(incremented, data, write_n, u) return destr