def test_layout_10_wo(self):
elem = Element(10, "w")
self.assertEqual(elem.width, 10)
self.assertEqual(elem.access, Element.Access.W)
self.assertEqual(elem.layout, Layout.cast([
("w_data", 10),
("w_stb", 1),
]))
def outlet(self, **kwargs):
return PipeOutlet(
self,
Layout((PipeOutlet.prefices[dir] + name, shape)
for (name, shape, dir) in self._signals()),
src_loc_at=1,
**kwargs,
)
def test_layout_1_ro(self):
elem = Element(1, "r")
self.assertEqual(elem.width, 1)
self.assertEqual(elem.access, Element.Access.R)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 1),
("r_stb", 1),
]))
def __init__(self, max_bits: int):
super().__init__(
Layout([
('dc', 1, Direction.FANIN),
('data', max_bits, Direction.FANIN),
('data_size', range(max_bits + 1), Direction.FANIN),
('start', 1, Direction.FANIN),
('done', 1, Direction.FANOUT),
]))
self.max_bits = max_bits
def test_layout_0_rw(self): # degenerate but legal case
elem = Element(0, access=Element.Access.RW)
self.assertEqual(elem.width, 0)
self.assertEqual(elem.access, Element.Access.RW)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 0),
("r_stb", 1),
("w_data", 0),
("w_stb", 1),
]))
def test_layout_8_rw(self):
elem = Element(8, access="rw")
self.assertEqual(elem.width, 8)
self.assertEqual(elem.access, Element.Access.RW)
self.assertEqual(elem.layout, Layout.cast([
("r_data", 8),
("r_stb", 1),
("w_data", 8),
("w_stb", 1),
]))
def test_layout(self):
iface = Interface(addr_width=12, data_width=8)
self.assertEqual(iface.addr_width, 12)
self.assertEqual(iface.data_width, 8)
self.assertEqual(iface.layout, Layout.cast([
("addr", 12),
("r_data", 8),
("r_stb", 1),
("w_data", 8),
("w_stb", 1),
]))
def __init__(self, width: int, reset=None):
if reset is not None:
fields = {'q': Signal(width, reset=reset)}
else:
fields = None
super().__init__(Layout([
('d', width, Direction.FANIN),
('q', width, Direction.FANOUT),
('clk_en', 1, Direction.FANIN),
]),
fields=fields)
def __init__(self, name: str = None):
super().__init__(
Layout([
("address", unsigned(16)),
("data_in", unsigned(8)),
("data_out", unsigned(8)),
("rw", unsigned(1)),
("vma", unsigned(1)),
("ba", unsigned(1)),
("nmi", unsigned(1)),
("irq", unsigned(1)),
]),
name=name,
)
def new(cls, dswol, *, flags=0):
"""
Create a PipeSpec.
The first arg is either the width of the data signal, the `Shape`
of the data signal, a `Layout` describing the data signal, or
a tuple of tuples that nMigen can coerce into a `Layout`.
The flags arg may include DATA_SIZE or START_STOP flags.
"""
# dsol: data shape or layout
# dwsol: data width, shape, or layout
if isinstance(dswol, (Shape, int)):
dsol = Shape.cast(dswol)
else:
dsol = Layout.cast(dswol)
return cls(flags, dsol)
def __init__(self, width: int, name_hint: Optional[str] = None):
layout = Layout([
('mosi_data', width, Direction.FANIN),
('miso_data', width, Direction.FANOUT),
('transfer_size', range(width + 1), Direction.FANIN),
('start', 1, Direction.FANIN),
('done', 1, Direction.FANOUT),
])
mkname = lambda name: f'{name}_{name_hint}' if name_hint else name
super().__init__(layout,
fields={
name: Signal(shape,
name=mkname(name),
reset=0)
for name, (shape, _) in layout.fields.items()
})
self.width = width
class Bus(Record):
"""Write-only SPI bus + data/command control line."""
LAYOUT = Layout([
('dc', 1, Direction.FANOUT),
('cs_n', 1, Direction.FANOUT),
('clk', 1, Direction.FANOUT),
('mosi', 1, Direction.FANOUT),
])
def __init__(self, **kwargs):
super().__init__(self.LAYOUT, fields=kwargs)
def SPIBus(self) -> spi.Bus:
"""Convert to a 10 MHz SPI bus handle."""
return spi.Bus(cs_n=self.cs_n,
clk=self.clk,
mosi=self.mosi,
miso=Signal(name='miso', reset=0),
freq_Hz=10_000_000)
class Bus(Record):
"""Single-lane bidirectional SPI bus with chip select."""
LAYOUT = Layout([
('cs_n', 1),
('clk', 1),
('mosi', 1),
('miso', 1),
])
def __init__(self, cs_n: Signal, clk: Signal, mosi: Signal, miso: Signal,
freq_Hz: int):
super().__init__(self.LAYOUT,
fields={
'cs_n': cs_n,
'clk': clk,
'mosi': mosi,
'miso': miso,
})
self.freq_Hz = freq_Hz
def selftest():
ps0 = PipeSpec(8)
assert ps0.data_width == 8
assert ps0.flags == 0
assert type(ps0.dsol) is Shape
assert ps0.dsol == unsigned(8)
assert ps0.start_stop is False
assert ps0.data_size is False
assert ps0.as_int == 8
pi0 = ps0.inlet()
assert isinstance(pi0, PipeInlet)
assert isinstance(pi0, Record)
assert isinstance(pi0, Value)
assert pi0.o_data.shape() == unsigned(8)
c0 = pi0.flow_to(ps0.outlet())
assert len(c0) == 3
assert repr(c0[0]) == '(eq (sig i_data) (sig pi0__o_data))'
assert repr(c0[1]) == '(eq (sig i_valid) (sig pi0__o_valid))'
assert repr(c0[2]) == '(eq (sig pi0__i_ready) (sig o_ready))'
ps1 = PipeSpec(signed(5), flags=DATA_SIZE)
assert ps1.data_width == 5
assert ps1.flags == DATA_SIZE
assert type(ps1.dsol) is Shape
assert ps1.dsol == signed(5)
assert ps1.start_stop is False
assert ps1.data_size is True
assert ps1.as_int == 256 + 5
pi1 = ps1.inlet()
assert isinstance(pi1, PipeInlet)
assert isinstance(pi1, Record)
assert isinstance(pi1, Value)
assert pi1.o_data.shape() == signed(5)
c1 = ps1.outlet().flow_from(pi1)
assert len(c1) == 4
ps2 = PipeSpec((('a', signed(4)), ('b', unsigned(2))), flags=START_STOP)
assert ps2.data_width == 6
assert ps2.flags == START_STOP
assert type(ps2.dsol) is Layout
assert ps2.dsol == Layout((('a', signed(4)), ('b', unsigned(2))))
assert ps2.start_stop is True
assert ps2.data_size is False
assert ps2.as_int == 512 + 6
pi2 = ps2.inlet()
assert isinstance(pi2, PipeInlet)
assert isinstance(pi2, Record)
assert isinstance(pi2, Value)
assert pi2.o_data.shape() == unsigned(4 + 2)
po2 = ps2.outlet()
assert isinstance(po2, PipeOutlet)
assert po2.i_data.shape() == unsigned(4 + 2)
c2 = pi2.flow_to(po2)
assert len(c2) == 5
ps3 = PipeSpec.from_int(START_STOP | DATA_SIZE | 10)
assert ps3.data_width == 10
assert ps3.flags == START_STOP | DATA_SIZE
assert type(ps3.dsol) is Shape
assert ps3.dsol == unsigned(10)
assert ps3.start_stop is True
assert ps3.data_size is True
assert ps3.as_int == 512 + 256 + 10
pi3 = ps3.inlet(name='inlet_3')
assert isinstance(pi3, PipeInlet)
assert isinstance(pi3, Record)
assert isinstance(pi3, Value)
assert pi3.o_data.shape() == unsigned(10)
inlet_3 = ps3.inlet()
po3 = ps3.outlet(name='outlet_3')
outlet_3 = ps3.outlet()
assert repr(pi3) == repr(inlet_3)
assert repr(po3) == repr(outlet_3)
assert repr(pi3.fields) == repr(inlet_3.fields)
assert repr(po3.fields) == repr(outlet_3.fields)
c3 = pi3.flow_to(po3)
c3a = outlet_3.flow_from(inlet_3)
assert len(c3) == 6
assert len(c3a) == 6
from nmigen.hdl.rec import Layout
from nmigen.lib.cdc import FFSynchronizer
from nmigen.lib.fifo import SyncFIFO
from nmigen.utils import bits_for
from elab import SimulationTestCase, rename_sync
import unittest
DoubleBufferReadLayout = Layout([
# Input: read next piece of data. Data available next cycle.
('next', 1),
# Output: data that has been read
('data', 16),
# Output: current data is last
('last', 1),
# Input: flip the read/write pointer. Takes effect next cycle.
('toggle', 1),
])
DoubleBufferWriteLayout = Layout([
# Output: the reader just toggled the pointer so buffer is ready
# for more input
('ready', 1),
# Input: write the provided data
('en', 1),
data = []
for i in range(128):
data.append(d[i])
return data
def build_mem(coding):
" Build the map and a memory block"
alpha = convert(coding)
layout(alpha)
mem = covert_to_init(alpha)
return alpha, mem
# define layouts
char_incoming = Layout([("data", 8)])
bitstream = Layout([("bitstream", 1)])
# elaboratable morse encoder
class Morse(Elaboratable):
" takes a byte stream and converts it to a morse bitstream "
def __init__(self, mapping):
# memory for the lookup table
self.enc = Memory(width=16, depth=128, init=mapping)
self.read = self.enc.read_port()
# incoming char
self.sink = stream.StreamSink(char_incoming)
# output bitstream
self.source = stream.StreamSource(bitstream)