def __init__(self, rom_file: str):
super().__init__()
self.rom_file = rom_file
self.segments = Signal(8)
self.anodes = Signal(8)
self.ibus = Record(wishbone.wishbone_layout)
self.dbus = Record(wishbone.wishbone_layout)
class Peripherals(Elaboratable):
def __init__(self, rom_file: str):
super().__init__()
self.rom_file = rom_file
self.segments = Signal(8)
self.anodes = Signal(8)
self.ibus = Record(wishbone.wishbone_layout)
self.dbus = Record(wishbone.wishbone_layout)
def elaborate(self, _: Optional[Platform]) -> Module:
m = Module()
# Set up ROM/RAM peripherals
m.submodules.rom = rom = XilinxDualPortBRAM(read_only=True,
init_file=self.rom_file)
m.submodules.ram = ram = XilinxDualPortBRAM()
# Set up the display peripheral
bank = seven_segment.DisplayBank()
m.d.comb += self.segments.eq(bank.segments)
m.d.comb += self.anodes.eq(bank.anodes)
m.submodules.sseg = sseg = SevenSegmentDisplay(bank)
# Connect peripherals to the instruction and data buses
m.d.comb += self.ibus.connect(rom.abus)
m.submodules.dmux = dmux = WishboneMux((
('rom', 0x00000000, 4 * 1024, rom.bbus),
('ram', 0x00001000, 4 * 1024, ram.abus),
('sseg', 0x00002000, 0x100, sseg.wbus),
))
m.d.comb += self.dbus.connect(dmux.wbus)
return m
def __init__(self,
*,
read_only: bool = False,
init_file: Optional[str] = None,
init: Optional[bytes] = None):
super().__init__()
self.read_only = read_only
self.bytes = self._init_bytes(init_file, init)
self.abus = Record(wishbone.wishbone_layout)
self.bbus = Record(wishbone.wishbone_layout)
def elaborate(self, _: Optional[Platform]) -> Module:
m = Module()
addressed_signals = []
for port in self.ports:
# Better debug naming
pbus = Record.like(port.wbus, name=port.name)
m.d.comb += pbus.connect(port.wbus)
mask32 = ~(port.size - 1)
mask30 = mask32 >> 2
addressed = Signal(name=f'addressed_{port.name}')
m.d.comb += addressed.eq((self.wbus.adr
& mask30) == port.start >> 2)
addressed_signals.append(addressed)
m.d.comb += [
pbus.adr.eq(self.wbus.adr),
pbus.dat_w.eq(self.wbus.dat_w),
pbus.sel.eq(self.wbus.sel),
pbus.stb.eq(self.wbus.stb),
pbus.we.eq(self.wbus.we),
pbus.cti.eq(self.wbus.cti),
pbus.bte.eq(self.wbus.bte),
]
with m.If(addressed):
m.d.comb += [
pbus.cyc.eq(self.wbus.cyc),
self.wbus.dat_r.eq(pbus.dat_r),
self.wbus.ack.eq(pbus.ack),
self.wbus.err.eq(pbus.err),
]
with m.If(self.wbus.cyc & ~Cat(*addressed_signals).any()):
m.d.comb += self.wbus.err.eq(1)
return m
def __init__(self):
# Create a stand-in for our UART.
self.uart_pins = Record([('rx', [('i', 1)]), ('tx', [('o', 1)])])
# Create our SoC...
self.soc = soc = SimpleSoC()
soc.add_rom("eptri_example.bin", 0x4000)
# ... add some bulk RAM ...
soc.add_ram(0x4000)
# ... add a UART ...
self.uart = uart = AsyncSerialPeripheral(divisor=int(60e6 // 115200),
pins=self.uart_pins)
soc.add_peripheral(uart)
# ... add a timer, to control our LED blinkies...
self.timer = timer = TimerPeripheral(24)
soc.add_peripheral(timer)
# ... a core USB controller ...
self.controller = USBDeviceController()
soc.add_peripheral(self.controller)
# ... and add our eptri peripherals.
self.setup = SetupFIFOInterface()
soc.add_peripheral(self.setup, as_submodule=False)
self.in_ep = InFIFOInterface()
soc.add_peripheral(self.in_ep, as_submodule=False)
self.out_ep = OutFIFOInterface()
soc.add_peripheral(self.out_ep, as_submodule=False)
def __init__(self,
size: int,
regs: Iterable['WishboneRegisters.RegLike'] = ()):
super().__init__()
self.size = size
self.registers = []
self.wbus = Record(wishbone.wishbone_layout)
self._by_name = {}
for reg in regs:
self.add_register(reg)
def __init__(self):
# Create a stand-in for our UART.
self.uart_pins = Record([('rx', [('i', 1)]), ('tx', [('o', 1)])])
# Create our SoC...
self.soc = soc = SimpleSoC()
soc.add_bios_and_peripherals(uart_pins=self.uart_pins)
# ... add some bulk RAM ...
soc.add_ram(0x4000)
# ... and add our LED peripheral.
leds = LEDPeripheral()
soc.add_peripheral(leds)
class SevenSegmentDisplay(Elaboratable):
def __init__(self, output: seven_segment.DisplayBank):
super().__init__()
self.output = output
self.wbus = Record(wishbone.wishbone_layout)
def elaborate(self, _: Optional[Platform]) -> Module:
m = Module()
m.submodules.regs = regs = WishboneRegisters(size=0x100,
regs=[('data', 0x00, 4,
0x0000_0000)])
m.d.comb += self.wbus.connect(regs.wbus)
m.submodules.digit = digit = seven_segment.HexDigitLUT()
digits = Array(regs.data[4 * i:4 * (i + 1)] for i in range(8))
m.submodules.mux = mux = seven_segment.DisplayMultiplexer(self.output)
m.d.comb += digit.input.eq(digits[mux.select])
m.d.comb += mux.segments.eq(digit.output)
m.d.comb += mux.duty_cycle.eq(-1)
return m
def __init__(self):
clock_freq = 60e6
# Create our SoC...
self.soc = soc = SimpleSoC()
soc.add_rom('hello_world.bin', size=0x1000)
soc.add_ram(0x1000)
# ... add our UART peripheral...
self.uart_pins = Record([('rx', [('i', 1)]), ('tx', [('o', 1)])])
self.uart = uart = AsyncSerialPeripheral(divisor=int(clock_freq //
115200),
pins=self.uart_pins)
soc.add_peripheral(uart)
# ... add a timer, to control our LED blinkies...
self.timer = timer = TimerPeripheral(24)
soc.add_peripheral(timer)
# ... and add our LED peripheral.
leds = LEDPeripheral()
soc.add_peripheral(leds)
def elaborate(self, platform):
m = Module()
frame = Record(_frame_layout)
bitno = self.bitno = Signal(range(12))
setup = Signal()
shift = Signal()
input = Signal()
with m.If(setup):
m.d.sync += self.bus.data_o.eq(frame[0])
with m.If(shift):
m.d.sync += [
frame.eq(Cat(frame[1:], input)),
bitno.eq(bitno + 1),
]
with m.FSM():
with m.State("IDLE"):
with m.If(self.en):
m.d.sync += [
*_prepare_frame(frame, self.i_data),
self.bus.clock_o.eq(1),
bitno.eq(0),
]
with m.If(self.i_valid):
m.d.comb += [
setup.eq(1),
shift.eq(1),
]
m.next = "SEND-BIT"
with m.Else():
m.next = "RECV-BIT"
with m.Else():
m.d.sync += [
# Inhibit clock
self.bus.clock_o.eq(0),
self.bus.data_o.eq(1),
]
with m.State("SEND-BIT"):
m.d.comb += [
input.eq(1),
setup.eq(self.bus.falling),
shift.eq(self.bus.rising),
]
with m.If(bitno == 12):
m.d.comb += self.stb.eq(1)
m.d.sync += [
bitno.eq(0),
# Device acknowledgement ("line control" bit)
self.i_ack.eq(~self.bus.data_i),
]
m.next = "RECV-BIT"
with m.If(~self.en):
m.next = "IDLE"
with m.State("RECV-BIT"):
m.d.comb += [
input.eq(self.bus.data_i),
shift.eq(self.bus.falling),
]
with m.If(bitno == 11):
m.d.comb += self.stb.eq(1),
m.d.sync += [
bitno.eq(0),
self.o_valid.eq(_verify_frame(frame)),
self.o_data.eq(frame.data),
]
with m.If(~self.en):
m.next = "IDLE"
return m
def __init__(self, output: seven_segment.DisplayBank):
super().__init__()
self.output = output
self.wbus = Record(wishbone.wishbone_layout)
def __init__(self, ports: Iterable['WishboneMux.PortLike'] = ()):
super().__init__()
self.ports = []
self.wbus = Record(wishbone.wishbone_layout)
for port in ports:
self.add_port(port)
def __init__(self, data_w, addr_w, **kargs):
layout = get_axilite_layout('slave', data_w, addr_w)
Record.__init__(self, layout, **kargs)
def __init__(self, data_w, addr_w, id_w, user_w=0, **kargs):
layout = get_axi_layout('master', data_w, addr_w, id_w, user_w)
Record.__init__(self, layout, **kargs)
def elaborate(self, platform):
m = Module()
m.submodules.output = output = VGAOutput(self.pads)
m.domains.pix = cd_pix = ClockDomain(reset_less=True)
m.submodules += PLL(f_in=platform.default_clk_frequency, f_out=self.pix_clk_freq, odomain="pix")
platform.add_clock_constraint(cd_pix.clk, self.pix_clk_freq)
h_total = self.h_front + self.h_sync + self.h_back + self.h_active
v_total = self.v_front + self.v_sync + self.v_back + self.v_active
h_ctr = Signal(range(h_total))
v_ctr = Signal(range(v_total))
pix = Record([
("r", 1),
("g", 1),
("b", 1),
])
h_en = Signal()
v_en = Signal()
h_stb = Signal()
v_stb = Signal()
m.d.comb += [
h_stb.eq(h_ctr == self.h_active),
v_stb.eq(h_stb & (v_ctr == self.v_active)),
]
with m.If(h_ctr == h_total - 1):
with m.If(v_ctr == v_total - 1):
m.d.pix += v_ctr.eq(0)
with m.Else():
m.d.pix += v_ctr.eq(v_ctr + 1)
m.d.pix += h_ctr.eq(0)
with m.Else():
m.d.pix += h_ctr.eq(h_ctr + 1)
with m.If(h_ctr == 0):
m.d.pix += h_en.eq(1)
with m.Elif(h_ctr == self.h_active):
m.d.pix += h_en.eq(0)
with m.Elif(h_ctr == self.h_active + self.h_front):
m.d.pix += output.hs.eq(1)
with m.Elif(h_ctr == self.h_active + self.h_front + self.h_sync):
m.d.pix += output.hs.eq(0)
with m.If(v_ctr == 0):
m.d.pix += v_en.eq(1)
with m.Elif(v_ctr == self.v_active):
m.d.pix += v_en.eq(0)
with m.Elif(v_ctr == self.v_active + self.v_front):
m.d.pix += output.vs.eq(1)
with m.Elif(v_ctr == self.v_active + self.v_front + self.v_sync):
m.d.pix += output.vs.eq(0)
with m.If(v_en & h_en):
m.d.pix += [
output.r.eq(pix.r),
output.g.eq(pix.g),
output.b.eq(pix.b),
]
with m.Else():
m.d.pix += [
output.r.eq(0),
output.g.eq(0),
output.b.eq(0),
]
m.d.comb += \
Cat(pix.r, pix.g, pix.b) \
.eq(h_ctr[5:] + v_ctr[5:])
return m