def __init__(self, *, reset_addr, clk_freq, rom_addr, rom_size, ram_addr,
ram_size, uart_addr, uart_divisor, uart_pins, timer_addr,
timer_width):
self._arbiter = wishbone.Arbiter(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self._decoder = wishbone.Decoder(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self.cpu = MinervaCPU(reset_address=reset_addr)
self._arbiter.add(self.cpu.ibus)
self._arbiter.add(self.cpu.dbus)
self.rom = SRAMPeripheral(size=rom_size, writable=False)
self._decoder.add(self.rom.bus, addr=rom_addr)
self.ram = SRAMPeripheral(size=ram_size)
self._decoder.add(self.ram.bus, addr=ram_addr)
self.uart = AsyncSerialPeripheral(divisor=uart_divisor, pins=uart_pins)
self._decoder.add(self.uart.bus, addr=uart_addr)
self.timer = TimerPeripheral(width=timer_width)
self._decoder.add(self.timer.bus, addr=timer_addr)
self.intc = GenericInterruptController(width=len(self.cpu.ip))
self.intc.add_irq(self.timer.irq, 0)
self.intc.add_irq(self.uart.irq, 1)
self.memory_map = self._decoder.bus.memory_map
self.clk_freq = clk_freq
def __init__(self, *, clk_freq,
ddrphy_addr, dramcore_addr,
ddr_addr):
self.crg = ECPIX5CRG()
self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})
ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "we_n":4, "odt":4, "ras":4, "cas":4, "we":4})
self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
ddrmodule = MT41K256M16(clk_freq, "1:2")
self.dramcore = DomainRenamer("dramsync")(gramCore(
phy=self.ddrphy,
geom_settings=ddrmodule.geom_settings,
timing_settings=ddrmodule.timing_settings,
clk_freq=clk_freq))
self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
self._decoder.add(self.drambone.bus, addr=ddr_addr)
self.memory_map = self._decoder.bus.memory_map
self.clk_freq = clk_freq
def __init__(self, *, clk_freq, dramcore_addr, ddr_addr):
self._decoder = wishbone.Decoder(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self.bus = wishbone.Interface(addr_width=30,
data_width=32,
granularity=8)
tck = 2 / (2 * 2 * 100e6)
nphases = 2
databits = 16
nranks = 1
addressbits = 14
bankbits = 3
cl, cwl = get_cl_cw("DDR3", tck)
cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl)
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
physettings = PhySettings(phytype="ECP5DDRPHY",
memtype="DDR3",
databits=databits,
dfi_databits=4 * databits,
nranks=nranks,
nphases=nphases,
rdphase=rdphase,
wrphase=wrphase,
rdcmdphase=rdcmdphase,
wrcmdphase=wrcmdphase,
cl=cl,
cwl=cwl,
read_latency=2 + cl_sys_latency + 2 +
log2_int(4 // nphases) + 4,
write_latency=cwl_sys_latency)
ddrmodule = MT41K256M16(clk_freq, "1:2")
self.ddrphy = FakePHY(module=ddrmodule,
settings=physettings,
verbosity=SDRAM_VERBOSE_DBG)
self.dramcore = gramCore(phy=self.ddrphy,
geom_settings=ddrmodule.geom_settings,
timing_settings=ddrmodule.timing_settings,
clk_freq=clk_freq)
self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
self.drambone = gramWishbone(self.dramcore)
self._decoder.add(self.drambone.bus, addr=ddr_addr)
self.memory_map = self._decoder.bus.memory_map
self.clk_freq = clk_freq
def __init__(self, *, ram_addr, ram_size, uart_addr, uart_divisor,
uart_pins):
self._arbiter = wishbone.Arbiter(addr_width=30,
data_width=32,
granularity=8)
self._decoder = wishbone.Decoder(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self.ram = SRAMPeripheral(size=ram_size)
self._decoder.add(self.ram.bus, addr=ram_addr)
self.bridge = UARTBridge(divisor=uart_divisor, pins=uart_pins)
def __init__(self, *,
uart_pins, ddr_pins,
ddrphy_addr, dramcore_addr,
ddr_addr):
self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})
self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})
freq = 100e6
self.crg = ECPIX5CRG()
self.cpu = MinervaCPU(reset_address=0)
self._arbiter.add(self.cpu.ibus)
self._arbiter.add(self.cpu.dbus)
self.intc = GenericInterruptController(width=len(self.cpu.ip))
self.rom = SRAMPeripheral(size=4096, writable=False)
with open("firmware/main.bin", "rb") as f:
words = iter(lambda: f.read(self.cpu.data_width // 8), b'')
bios = [int.from_bytes(w, self.cpu.byteorder) for w in words]
self.rom.init = bios
self._decoder.add(self.rom.bus, addr=0)
self.ram = SRAMPeripheral(size=4096)
self._decoder.add(self.ram.bus, addr=0x1000)
self.uart = AsyncSerialPeripheral(divisor=int(freq//115200), pins=uart_pins)
self._decoder.add(self.uart.bus, addr=0x2000)
self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
ddrmodule = MT41K256M16(freq, "1:2")
self.dramcore = DomainRenamer("dramsync")(gramCore(
phy=self.ddrphy,
geom_settings=ddrmodule.geom_settings,
timing_settings=ddrmodule.timing_settings,
clk_freq=freq))
self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
self._decoder.add(self.drambone.bus, addr=ddr_addr)
self.memory_map = self._decoder.bus.memory_map
self.clk_freq = freq
def __init__(self, clock_frequency=int(60e6)):
"""
Parameters:
clock_frequency -- The frequency of our `sync` domain, in MHz.
"""
self.clk_freq = clock_frequency
self._main_rom = None
self._main_ram = None
self._uart_baud = None
# Keep track of our created peripherals and interrupts.
self._submodules = []
self._irqs = {}
self._next_irq_index = 0
# By default, don't attach any debug hardware; or build a BIOS.
self._auto_debug = False
self._build_bios = False
#
# Create our core hardware.
# We'll create this hardware early, so it can be used for e.g. code generation without
# fully elaborating our design.
#
# Create our CPU.
self.cpu = MinervaCPU(with_debug=True)
# Create our interrupt controller.
self.intc = GenericInterruptController(width=32)
# Create our bus decoder and set up our memory map.
self.bus_decoder = wishbone.Decoder(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self.memory_map = self.bus_decoder.bus.memory_map
def __init__(self, periph, *, data_width, granularity, features,
alignment):
if not isinstance(periph, Peripheral):
raise TypeError(
"Peripheral must be an instance of Peripheral, not {!r}".
format(periph))
self._wb_decoder = wishbone.Decoder(addr_width=1,
data_width=data_width,
granularity=granularity,
features=features,
alignment=alignment)
self._csr_subs = []
for bank, bank_addr, bank_alignment in periph.iter_csr_banks():
if bank_alignment is None:
bank_alignment = alignment
csr_mux = csr.Multiplexer(addr_width=1,
data_width=8,
alignment=bank_alignment)
for elem, elem_addr, elem_alignment in bank.iter_csr_regs():
if elem_alignment is None:
elem_alignment = alignment
csr_mux.add(elem,
addr=elem_addr,
alignment=elem_alignment,
extend=True)
csr_bridge = WishboneCSRBridge(csr_mux.bus, data_width=data_width)
self._wb_decoder.add(csr_bridge.wb_bus,
addr=bank_addr,
extend=True)
self._csr_subs.append((csr_mux, csr_bridge))
for window, window_addr, window_sparse in periph.iter_windows():
self._wb_decoder.add(window,
addr=window_addr,
sparse=window_sparse,
extend=True)
events = list(periph.iter_events())
if len(events) > 0:
self._int_src = InterruptSource(events,
name="{}_ev".format(periph.name))
self.irq = self._int_src.irq
csr_mux = csr.Multiplexer(addr_width=1,
data_width=8,
alignment=alignment)
csr_mux.add(self._int_src.status, extend=True)
csr_mux.add(self._int_src.pending, extend=True)
csr_mux.add(self._int_src.enable, extend=True)
csr_bridge = WishboneCSRBridge(csr_mux.bus, data_width=data_width)
self._wb_decoder.add(csr_bridge.wb_bus, extend=True)
self._csr_subs.append((csr_mux, csr_bridge))
else:
self._int_src = None
self.irq = None
self.bus = self._wb_decoder.bus