def test_stress_meld_16(self): """ Check that we can combine 0-15 to create a /4 mask """ TA = "A" a = Match([('IN_PORT', 0, 0x1f)]) u_bdd = wc_to_BDD(a.get_wildcard(), TA, TA) rng = [4, 14, 9, 2, 5, 10, 7, 8, 12, 13, 3, 6, 15, 1, 11] for i in rng: m = Match([('IN_PORT', i, 0x1f)]) m_bdd = wc_to_BDD(m.get_wildcard(), TA, TA) n_bdd = u_bdd + m_bdd # Check the result of the opposite works, as these are # non-overlapping sections self.assertEqual(n_bdd, (m_bdd + u_bdd)) u_bdd = n_bdd r = Match([('IN_PORT', 0, 0x10)]) r_bdd = wc_to_BDD(r.get_wildcard(), TA, TA) # The 16 exact matches, should have combined into a single range self.assertEqual(u_bdd, r_bdd)
def test_bit_order(self): """ Matches within a field will be prefix matching. As such ensure that we are encoding the MSB in the highest node. This will result in smaller tables, and faster build times. """ # Adding 0101/4 -> A and 1000/2 -> B # * # 0/ \1 # * * # \1 0/ # * B # 0/ # * # \1 # A # Total of 7 nodes inc. terminals # We expect this ordering a = Match([("IPV4_SRC", 0x5, 0xF)]) b = Match([("IPV4_SRC", 0x8, 0xC)]) TA = "A" TB = "B" bdd_a = wc_to_BDD(a.get_wildcard(), TA, TA) bdd_b = wc_to_BDD(b.get_wildcard(), TB, TB) res = bdd_a + bdd_b self.assertEqual(len(res), 7) print(len(res)) # Adding the opposite 1010/4 -> A and 0001/1100 # Results in 8 nodes. a = Match([("IPV4_SRC", 0xA, 0xF)]) b = Match([("IPV4_SRC", 0x1, 0x3)]) TA = "A" TB = "B" bdd_a = wc_to_BDD(a.get_wildcard(), TA, TA) bdd_b = wc_to_BDD(b.get_wildcard(), TB, TB) res = bdd_a + bdd_b self.assertEqual(len(res), 8) print(len(res))
def test_stress_meld_66535(self): """ Check that we can combine 0-66535 to create a /16 mask """ TA = "A" a = Match([('IN_PORT', 0, 0x1ffff)]) u_bdd = wc_to_BDD(a.get_wildcard(), TA, TA) rng = range(1, 65536) random.seed(0) random.shuffle(list(rng)) for i in rng: m = Match([('IN_PORT', i, 0x1ffff)]) m_bdd = wc_to_BDD(m.get_wildcard(), TA, TA) n_bdd = u_bdd + m_bdd # Check the result of the opposite works, as these are # non-overlapping sections self.assertEqual(n_bdd, (m_bdd + u_bdd)) u_bdd = n_bdd r = Match([('IN_PORT', 0, 0x10000)]) r_bdd = wc_to_BDD(r.get_wildcard(), TA, TA) # The 16 exact matches, should have combined into a single range self.assertEqual(u_bdd, r_bdd)
def test_conversion_to_from_BDD(self): a = Match([("IPV4_SRC", 0x5, 0xF)]) TA = "A" bdd_a = wc_to_BDD(a.get_wildcard(), TA, TA) res = list(BDD_to_wcs(bdd_a)) self.assertEqual(len(res), 1) self.assertEqual(res[0][0], a.get_wildcard()) # Check the first and last fields for off by 1 issues # Purposely checking 0xF on the ends as this ensures no off by one # error missing a bit # Check this first field a = Match([(self.OF.ordered_oxm_fields[0], 0xF445FA82FF38F92F, None)]) TA = "A" bdd_a = wc_to_BDD(a.get_wildcard(), TA, TA) res = list(BDD_to_wcs(bdd_a)) self.assertEqual(len(res), 1) self.assertEqual(res[0][0], a.get_wildcard()) # Check the last field a = Match([(self.OF.ordered_oxm_fields[-1], 0xF445FA82FF38F92F, None)]) TA = "A" bdd_a = wc_to_BDD(a.get_wildcard(), TA, TA) res = list(BDD_to_wcs(bdd_a)) self.assertEqual(len(res), 1) self.assertEqual(res[0][0], a.get_wildcard())