def get_buffers(self, handle):
"""get_buffers gets the three basic buffers needed for test.
dsm (device status memory), src (source or input),
and dst (destination or output).
:param handle: Use given handle for allocating buffers and preparing
for use with accelerator
"""
bsize = self.buffer_size()
dsm = fpga.allocate_shared_buffer(handle, int(KiB(4)))
# allocate the smallest possible workspace for DSM, SRC, DST
scratch = None
if KiB(2) >= bsize or (KiB(4) < bsize
and MiB(1) >= bsize) or (MiB(2) < bsize
and MiB(512) > bsize):
scratch = fpga.allocate_shared_buffer(handle, bsize * 2)
src, dst = scratch.split(bsize, bsize)
else:
src = fpga.allocate_shared_buffer(handle, bsize)
dst = fpga.allocate_shared_buffer(handle, bsize)
return (dsm, src, dst)
def cool_fpga_cache(self, handle, dsm):
ice = fpga.allocate_shared_buffer(handle, COOL_CACHE_SIZE)
dsm.fill(0)
ctl = nlb.CTL(width=32)
cfg = nlb.CFG(width=32)
self.logger.info("cooling fpga cache for mode: %s", self.args.mode)
self.write_csr64(handle, self.DSM_ADDR, dsm.io_address())
self.write_csr32(handle, ctl.offset(), ctl.value(reset=0))
self.write_csr32(handle, ctl.offset(), ctl.value(reset=1))
self.write_csr64(handle, self.SRC_ADDR, cl_align(ice.io_address()))
self.write_csr32(handle, self.NUM_LINES, COOL_CACHE_LINES)
cfg_offset = cfg.offset()
cfg_value = cfg.value(mode=int(self.modes["read"]),
rd_chsel=int(self.rd_chsel("vl0")),
cache_hint=int(self.cache_hint("rdline-I")))
self.write_csr32(handle, cfg_offset, cfg_value)
self.write_csr32(handle, ctl.offset(), ctl.value(reset=1, start=1))
if not self.wait_for_dsm(dsm):
raise RuntimeError("DSM Complete timeout during cool fpga cache")
self.write_csr32(handle, ctl.offset(),
ctl.value(stop=1, reset=1, start=1))
self.logger.info("fpga cache cooled")
import time
from opae import fpga
NLB0 = "C6AA954A-9B91-4A37-ABC1-1D9F0709DCC3"
def cl_align(addr):
return addr >> 6
tokens = fpga.enumerate(type=fpga.ACCELERATOR, guid=NLB0)
assert tokens, "Could not enumerate accelerator: {}".format(NlB0)
with fpga.open(tokens[0], fpga.OPEN_SHARED) as handle:
src = fpga.allocate_shared_buffer(handle, 4096)
dst = fpga.allocate_shared_buffer(handle, 4096)
handle.write_csr64(0x1018, cl_align(src.io_address())) # cacheline-aligned
handle.write_csr64(0x1020, cl_align(dst.io_address())) # cacheline-aligned
handle.write_csr32(0x1028, 4096)
r32_val = handle.read_csr32(0x1004)
while r32_val & 0x2 != 0x2:
time.sleep(0.001)
r32_val = handle.read_csr32(0x1004)