def __init__(s, SchedulerVRTL, src_msgs, sink_msgs, stall_prob, latency, src_delay, sink_delay, dump_vcd=False, test_verilog=False): # Instantiate Models s.src = TestSource(pageRankReqMsg(), src_msgs, src_delay) s.di = SchedulerVRTL s.sink = TestSink(pageRankRespMsg(), sink_msgs, sink_delay) s.mem = TestMemory(MemMsg(8, 32, 32), 1, stall_prob, latency) # Dump VCD if dump_vcd: s.di.vcd_file = dump_vcd # Translation if test_verilog: s.di = TranslationTool(s.di) # Connect s.connect(s.src.out, s.di.direq) s.connect(s.di.diresp, s.sink.in_) s.connect(s.di.memreq, s.mem.reqs[0]) s.connect(s.di.memresp, s.mem.resps[0])
def __init__( s, SchedulerVRTL, src_msgs, sink_msgs, stall_prob, latency, src_delay, sink_delay, dump_vcd=False, test_verilog=False ): # Instantiate Models s.src = TestSource ( pageRankReqMsg(), src_msgs, src_delay ) s.di = SchedulerVRTL s.sink = TestSink ( pageRankRespMsg(), sink_msgs, sink_delay ) s.mem = TestMemory ( MemMsg(8,32,32), 2, stall_prob, latency ) # Dump VCD if dump_vcd: s.di.vcd_file = dump_vcd # Translation if test_verilog: s.di = TranslationTool( s.di ) # Connect s.connect( s.src.out, s.di.direq ) s.connect( s.di.diresp, s.sink.in_ ) s.connect( s.di.memreq[0], s.mem.reqs[0] ) s.connect( s.di.memresp[0], s.mem.resps[0] ) s.connect( s.di.memreq[1], s.mem.reqs[1] ) s.connect( s.di.memresp[1], s.mem.resps[1] )
def resp(type, data): msg = pageRankRespMsg() if type == "rd": msg.type_ = pageRankReqMsg.TYPE_READ if type == "wr": msg.type_ = pageRankReqMsg.TYPE_WRITE msg.data = data return msg
def resp( type, data ): msg = pageRankRespMsg() if type == 'rd': msg.type_ = pageRankReqMsg.TYPE_READ if type == 'wr': msg.type_ = pageRankReqMsg.TYPE_WRITE msg.data = data return msg